`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 17:42 11/14/2019 // Design Name: // Module Name: RecvTop // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module RecvTop ( input clk, input clk2, input clk_60M_mac, input clk_4x, input rst, input rst2, input [11:0] dini, input [11:0] dinq, output [3:0] ad9361_ctrl_in, output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕 output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐 input [6:0] vio_stopbit, //寻找停止位，默认值为7'd60 //debug //trigger output rst_TimeSync, output rst_freq, output DAGC_rdy, output framesync, //帧同步峰 output framesync_delay, //帧同步峰，与频率补偿输出对应 output framesync_tsync, //帧同步标志，与TSync输出对应 output IntpARdy, //TSync输出nd output nd_SC_FDE_dout, //SC_FDE输出nd output framerdy, //一帧译码结果存储完毕标志 output reg flag_bercount = 1'd0, output reg flag_badframe = 1'd0, output reg flag_ber = 1'd0, //各模块输出，星座图 output [11:0] dc_removal_dout_i, //MGC_adaptation、去直流输出 output [11:0] dc_removal_dout_q, output [ 9:0] matchfilterout_i, //MF输出 output [ 9:0] matchfilterout_q, output [ 9:0] DAGC_out_i, //DAGC输出 output [ 9:0] DAGC_out_q, output [ 9:0] freqdataout_i, //频率补偿输出 output [ 9:0] freqdataout_q, output [ 9:0] IntpOuti, //TSync输出 output [ 9:0] IntpOutq, output [ 9:0] SC_FDE_douti, //SC_FDE输出 output [ 9:0] SC_FDE_doutq, //MGC_adaptation output [24:0] mean_temp, output [12:0] acc_mean, output [ 4:0] state_mgc, output mgc1_rdy, output flag_state_mgc, output [ 2:0] state_rst, output flag_overflow, output flag_small, //DC output [11:0] dc_value_i, output [11:0] dc_value_q, output flag_dc, //DAGC output flag_agch, output flag_agcl, output flag_agc_power, output [12:0] agc_ref, output [12:0] agc_check, //power test output flag_powerabsh, output flag_powerabsl, output flag_abs_power, output [10:0] abs_ref, output [10:0] abs_check, //TSync output [ 3:0] flag_clk_4bit, //位同步选取通道结果 //SC_FDE,溢出标志 output flagoverflow_fftpilot_26to14, //第1个fft结果截位，即导频fft结果的截位，26截到14 output flagoverflow_ChnZF_26to18, //第2个fft结果截位，即ZF信道估计结果的截位，26截到18 output flagoverflow_comdiv_34to20i, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18 output flagoverflow_comdiv_34to20q, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18 output flagoverflow_ifftzero_29to17i, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17 output flagoverflow_ifftzero_29to17q, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17 output flagoverflow_MMSEdiv_divisor_31to28, //第2个除法器，即MMSE除法的分母截位，31截到28 output flagoverflow_divmmse_34to11, //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11 output flagoverflow_ifftindata_28to20i, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20 output flagoverflow_ifftindata_28to20q, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20 output flagoverflow_fftdata_26to16i, //数据段ow的fft输出截位，26截到16 output flagoverflow_fftdata_26to16q, //数据段ow的fft输出截位，26截到16 output flagoverflow_FDE_dataout_29to10i, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10 output flagoverflow_FDE_dataout_29to10q, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10 output reg flagoverflow = 1'd0, //总溢出标志 output Pilot_rdy_hide1_d1, output [63:0] recvNetData, output recvNetDataNd, input debug_loss ); reg [7:0] cnt_mgc_delay; wire mgc_start; wire flag_mgc_done; // level flag wire flag_mgc_done_4x; // level flag always @(posedge clk) begin if (rst) begin cnt_mgc_delay <= 0; end else if (cnt_mgc_delay < 8'hff) begin cnt_mgc_delay <= cnt_mgc_delay + 1; end else begin cnt_mgc_delay <= cnt_mgc_delay; end end assign mgc_start = (cnt_mgc_delay == 8'hFE); ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl ( .clk (clk), .rst (rst), .start (mgc_start), .rx_data_i (dini), .rx_data_q (dinq), .ad9361_ctrl_in(ad9361_ctrl_in), .flag_mgc_done (flag_mgc_done) ); reg MF_rdy; // flag_mgc_done_d1 wire MF_rst; // flag_mgc_done_pulse_d2 always @(posedge clk) begin if (rst) begin MF_rdy <= 0; end else begin MF_rdy <= flag_mgc_done; end end wire fifo_out_valid; reg [ 2:0] cnt_fifo_out_valid; reg [ 2:0] cnt_fifo_out_valid_sel = 1; // 根据speed mode对应的计数器边界值 wire [31:0] fifo_out; reg dmf_s_valid; wire dmf_tvalid_interp4_i; wire dmf_tvalid_interp4_q; wire [31:0] mf_data_interp4_i; wire [31:0] mf_data_interp4_q; wire [23:0] dmf_tdata_interp4_i; wire [23:0] dmf_tdata_interp4_q; // valid signal for dmf always @(posedge clk_4x) begin if (rst) begin dmf_s_valid <= 1'd0; end else if (flag_mgc_done_4x && fifo_out_valid && cnt_fifo_out_valid == cnt_fifo_out_valid_sel) begin // fifo_out_valid may be not trustable at the rst state dmf_s_valid <= 1'd1; end else begin dmf_s_valid <= 1'd0; end end always @(posedge clk_4x) begin if (rst) begin cnt_fifo_out_valid <= 3'd0; end else if (fifo_out_valid) begin if (cnt_fifo_out_valid == cnt_fifo_out_valid_sel) begin // refer to Receiver.v cnt_fifo_out_valid <= 3'd0; end else begin cnt_fifo_out_valid <= cnt_fifo_out_valid + 3'd1; end end else begin cnt_fifo_out_valid <= cnt_fifo_out_valid; end end // Match filter fir_match_interp4 u_fir_match_filter_interp4_i ( .aclk (clk), // input wire aclk .s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid .s_axis_data_tready(), // output wire s_axis_data_tready .s_axis_data_tdata ({4'd0, dini}), // input wire [15 : 0] s_axis_data_tdata .m_axis_data_tvalid(), // output wire m_axis_data_tvalid .m_axis_data_tdata (mf_data_interp4_i) // output wire [31 : 0] m_axis_data_tdata ); fir_match_interp4 u_fir_match_filter_interp4_q ( .aclk (clk), // input wire aclk .s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid .s_axis_data_tready(), // output wire s_axis_data_tready .s_axis_data_tdata ({4'd0, dinq}), // input wire [15 : 0] s_axis_data_tdata .m_axis_data_tvalid(), // output wire m_axis_data_tvalid .m_axis_data_tdata (mf_data_interp4_q) // output wire [31 : 0] m_axis_data_tdata ); // CDC into clk_4x fifo_shift u_fifo_shift ( // input .s_aclk (clk), // input wire s_aclk .s_aresetn (flag_mgc_done), // input wire s_aresetn .s_axis_tvalid(flag_mgc_done), // input wire s_axis_tvalid .s_axis_tready(), // output wire s_axis_tready .s_axis_tdata ({8'd0, mf_data_interp4_q[29-:12], mf_data_interp4_i[29-:12]}), // input wire [31 : 0] s_axis_tdata // output .m_aclk (clk_4x), // input wire m_aclk .m_axis_tvalid(fifo_out_valid), // output wire m_axis_tvalid .m_axis_tready(1'b1), // input wire m_axis_tready .m_axis_tdata (fifo_out), // output wire [31 : 0] m_axis_tdata .wr_rst_busy (), .rd_rst_busy () ); fir_dmf_interp4 u_fir_dmf_interp4_i ( .aclk (clk_4x), .s_axis_data_tvalid(dmf_s_valid), .s_axis_data_tready(), .s_axis_data_tdata ({4'd0, fifo_out[11:0]}), .m_axis_data_tvalid(dmf_tvalid_interp4_i), .m_axis_data_tdata (dmf_tdata_interp4_i) ); fir_dmf_interp4 u_fir_dmf_interp4_q ( .aclk (clk_4x), .s_axis_data_tvalid(dmf_s_valid), .s_axis_data_tready(), .s_axis_data_tdata ({4'd0, fifo_out[23:12]}), .m_axis_data_tvalid(dmf_tvalid_interp4_q), .m_axis_data_tdata (dmf_tdata_interp4_q) ); wire [21:0] mag; wire mag_valid; wire frame_sync_4x; wire frame_sync_pulse; // in domain clk reg flag_frame_sync; // active high level // calc the magnitude MagnitudeEstimator #( .VEC_WIDTH(21) ) u_MagnitudeEstimator ( .clk (clk_4x), .rst (rst), .vec_valid(dmf_tvalid_interp4_i), .I (dmf_tdata_interp4_i), .Q (dmf_tdata_interp4_q), .mag (mag), .mag_valid(mag_valid) ); // frame sync threashold judgement PAPR #( .MAG_WIDTH (22), .WINDOW_DEPTH(1023) ) u_PAPR ( .clk (clk_4x), .rst (rst), .vec_mag (mag), .mag_valid (mag_valid), .frame_sync (frame_sync_4x), .frame_sync_pulse() ); always @(posedge clk) begin if (rst) begin flag_frame_sync <= 0; end else if (frame_sync_pulse) begin flag_frame_sync <= 1; end else begin flag_frame_sync <= flag_frame_sync; end end // wire [9:0] DAGC_out_i; // wire [9:0] DAGC_out_q; wire [9:0] FrameSync_douti; wire [9:0] FrameSync_doutq; wire dagc_rdy; wire mgc_rdy; wire rst_dagc; //帧同步模块 assign FrameSync_dini = DAGC_out_i; assign FrameSync_dinq = DAGC_out_q; // wire framesync; // * lost the connection with other nodes reg [20:0] cnt_lost; reg framelost; always @(posedge clk) begin if (Pilot_rdy_hide1_d1) begin cnt_lost <= 21'd0; framelost <= 1'b0; end else begin if (cnt_lost >= 21'd750000) begin cnt_lost <= 21'd0; framelost <= 1'b1; end else begin cnt_lost <= 21'd1 + cnt_lost; framelost <= 1'b0; end end end DAGC_v2 DAGC_v2 ( .clk (clk), .rst (~flag_mgc_done), .mgc1_rdy (MF_rdy), .framesync_d0 (flag_frame_sync), .vio_powertest_h (2'b00), .vio_powertest_l (2'b00), .matchfilterout_i(mf_data_interp4_i[29-:10]), // input, .matchfilterout_q(mf_data_interp4_q[29-:10]), // input .DAGC_out_i (DAGC_out_i), // output .DAGC_out_q (DAGC_out_q), // output // debug .flag_agch (flag_agch), .flag_agcl (flag_agcl), .flag_agc_power (flag_agc_power), .agc_ref (agc_ref), .agc_check (agc_check), .dagc_rdy (dagc_rdy), .mgc_rdy (mgc_rdy), .rst_dagc (rst_dagc) ); //载波频偏补偿 // wire [9:0] freqdataout_i; // wire [9:0] freqdataout_q; // wire framesync_delay; wire data_save; //debug用，暂不需使用 // wire rst_freq; freqestm freqestm ( .clk (clk), .rst (mgc_start), .mgc_rdy (mgc_rdy), .framesync (dagc_rdy), .datain_i (DAGC_out_i), .datain_q (DAGC_out_q), .dataout_i (freqdataout_i), .dataout_q (freqdataout_q), .framesync_delay(framesync_delay), .data_save (data_save), .rst_freq (rst_freq) ); //位同步 wire [1:0] cnt_tsync; // wire framesync_tsync; //帧同步标志 TimeSync_top TimeSync_top ( .clk (clk), .rst (Pilot_rdy_hide1_d1), .dini (freqdataout_i), .dinq (freqdataout_q), .rdy (IntpARdy), .douti (IntpOuti), .doutq (IntpOutq), .vio_tsync_inter16(vio_tsync_inter16), .framesync (framesync_delay), //帧同步标志 .framesync_tsync (framesync_tsync), //帧同步标志 //debug .cnt_tsync (cnt_tsync), .flag_clk_4bit (flag_clk_4bit) ); // SC-FDE SC_FDE_TOP SC_FDE_TOP_djy ( .clk(clk), .rst(Pilot_rdy_hide1_d1), .EQUenable_vio(EQUenable_vio), //为1时启用均衡 .Zerozone_vio (Zerozone_vio), //零域估计，默认值为8'd29 .flag_ow_left (framesync_tsync), //在一帧内，与第一个数据段的pilot的ow第一个nd对齐 .nd (IntpARdy), .dini (IntpOuti), .dinq (IntpOutq), .nd_SC_FDE_dout (nd_SC_FDE_dout), .SC_FDE_douti (SC_FDE_douti), .SC_FDE_doutq (SC_FDE_doutq), // debug,溢出标志 .flagoverflow_fftpilot_26to14 (flagoverflow_fftpilot_26to14), .flagoverflow_ChnZF_26to18 (flagoverflow_ChnZF_26to18), .flagoverflow_comdiv_34to20i (flagoverflow_comdiv_34to20i), .flagoverflow_comdiv_34to20q (flagoverflow_comdiv_34to20q), .flagoverflow_ifftzero_29to17i (flagoverflow_ifftzero_29to17i), .flagoverflow_ifftzero_29to17q (flagoverflow_ifftzero_29to17q), .flagoverflow_MMSEdiv_divisor_31to28(flagoverflow_MMSEdiv_divisor_31to28), .flagoverflow_divmmse_34to11 (flagoverflow_divmmse_34to11), .flagoverflow_ifftindata_28to20i (flagoverflow_ifftindata_28to20i), .flagoverflow_ifftindata_28to20q (flagoverflow_ifftindata_28to20q), .flagoverflow_fftdata_26to16i (flagoverflow_fftdata_26to16i), .flagoverflow_fftdata_26to16q (flagoverflow_fftdata_26to16q), .flagoverflow_FDE_dataout_29to10i (flagoverflow_FDE_dataout_29to10i), .flagoverflow_FDE_dataout_29to10q (flagoverflow_FDE_dataout_29to10q) ); wire phase_adjust_rdy; wire [9:0] phase_adjust_douti; wire [9:0] phase_adjust_doutq; phase_adjust phase_adjust ( .clk (clk), .rst (Pilot_rdy_hide1_d1), .din_i (SC_FDE_douti), .din_q (SC_FDE_doutq), .nd (nd_SC_FDE_dout), .framesync(framesync_tsync), .rdy (phase_adjust_rdy), .dout_i (phase_adjust_douti), .dout_q (phase_adjust_doutq) ); wire IQmergerdy; wire ldpcsyncin; wire [7:0] IQmergedout; IQmerge IQmerge ( .clk (clk), .clk2 (clk2), .rst (rst2 || Pilot_rdy_hide1_d1), .nd (phase_adjust_rdy), .framesync (framesync_tsync), .dini (phase_adjust_douti), .dinq (phase_adjust_doutq), .rdy (IQmergerdy), .ldpcsyncin(ldpcsyncin), .dout (IQmergedout) ); wire LDPC_SyncOut; wire LDPC_Rdy; wire LDPC_Dout; wire [8:0] good_frames; wire [8:0] bad_frames; wire [8:0] total_frames; CCSDS_LDPC_DEC_K1024_R12_TOPP LDPC_decode ( .clk (clk2), .Rst (rst2 || Pilot_rdy_hide1_d1), .FrameSync (ldpcsyncin), .Nd (IQmergerdy), .Din (IQmergedout), .LDPC_SyncOut(LDPC_SyncOut), .Rdy (LDPC_Rdy), .LDPC_Dout (LDPC_Dout), .good_frames (good_frames), .bad_frames (bad_frames), .total_frames(total_frames) ); wire flag_notbyte; //为1时说明得到的有效数据不以字节为单位 wire [ 1:0] state_ram; wire berstart_1d; wire bercompare; wire [16:0] bercount; wire [16:0] bercount_max; wire [16:0] ROMaddra_d2; wire RAMdout_d1; wire validnd_new_new; wire [63:0] stop_temp_new; wire flag_stop_0; //给shx，拉高1个clk表示当前时帧有效数据接收完毕 wire [16:0] addr_stop_0; wire [ 2:0] cnt_8; wire state_8; wire rdy_scramble; wire dout_scramble; wire [16:0] RAMaddra; //比较误码率 wire [16:0] ROMaddra; //比较误码率 wire nd_ber; FrameMerge FrameMerge ( .clk (clk2), .rst (Pilot_rdy_hide1_d1), .rst2(rst2), .sync(LDPC_SyncOut), .nd (LDPC_Rdy), .din (LDPC_Dout), .vio_stopbit(vio_stopbit), .frameIDnd(Pilot_rdy_hide1_d1), .clk2 (clk_60M_mac), .framerdy (framerdy), .recv_addr_new_0 (recv_addr_new_0), .recv_addr_new_1 (recv_addr_new_1), .recv_addr_new_2 (recv_addr_new_2), .recv_addr_new_3 (recv_addr_new_3), .recv_data_new_0 (recv_data_new_0), .recv_data_new_1 (recv_data_new_1), .recv_data_new_2 (recv_data_new_2), .recv_data_new_3 (recv_data_new_3), .RAMaddra_write_0(RAMaddra_write_0), .RAMaddra_write_1(RAMaddra_write_1), .RAMaddra_write_2(RAMaddra_write_2), .RAMaddra_write_3(RAMaddra_write_3), .RAMaddra_new_0 (RAMaddra_new_0), .RAMaddra_new_1 (RAMaddra_new_1), .RAMaddra_new_2 (RAMaddra_new_2), .RAMaddra_new_3 (RAMaddra_new_3), .flag_notbyte(flag_notbyte), .state_ram (state_ram), .flag_stop (flag_stop), //给shx，拉高8个clk表示当前时帧有效数据接收完毕 .addr_stop (addr_stop), //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐 //debug .berstart_1d (berstart_1d), .bercompare (bercompare), .bercount (bercount), .bercount_max(bercount_max), .ROMaddra_d2 (ROMaddra_d2), .RAMdout_d1 (RAMdout_d1), .validnd_new_new(validnd_new_new), .stop_temp_new(stop_temp_new), .flag_stop_0(flag_stop_0), .addr_stop_0(addr_stop_0), .cnt_8 (cnt_8), .state_8 (state_8), .rdy_scramble (rdy_scramble), .dout_scramble(dout_scramble), .RAMaddra (RAMaddra), .ROMaddra (ROMaddra), .nd_ber (nd_ber), .recvNetData (recvNetData), .recvNetDataNd(recvNetDataNd) ); // ***** cdc ***** xpm_cdc_single #( .DEST_SYNC_FF (2), // DECIMAL; range: 2-10 .INIT_SYNC_FF (1), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values .SIM_ASSERT_CHK(1), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages .SRC_INPUT_REG (1) // DECIMAL; 0=do not register input, 1=register input ) xpm_cdc_startup_inst ( .dest_out(flag_mgc_done_4x), // 1-bit output: src_in synchronized to the destination clock domain. This output is // registered. .dest_clk(clk_4x), // 1-bit input: Clock signal for the destination clock domain. .src_clk (clk), // 1-bit input: optional; required when SRC_INPUT_REG = 1 .src_in (flag_mgc_done) // 1-bit input: Input signal to be synchronized to dest_clk domain. ); xpm_cdc_pulse #( .DEST_SYNC_FF (4), // DECIMAL; range: 2-10 .INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values .REG_OUTPUT (0), // DECIMAL; 0=disable registered output, 1=enable registered output .RST_USED (0), // DECIMAL; 0=no reset, 1=implement reset .SIM_ASSERT_CHK(1) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages ) xpm_cdc_frame_sync_pulse_inst ( .dest_pulse(frame_sync_pulse), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse // transfer is correctly initiated on src_pulse input. This output is // combinatorial unless REG_OUTPUT is set to 1. .dest_clk (clk), // 1-bit input: Destination clock. .dest_rst (), // 1-bit input: optional; required when RST_USED = 1 .src_clk (clk_4x), // 1-bit input: Source clock. .src_pulse (frame_sync_4x), // 1-bit input: Rising edge of this signal initiates a pulse transfer to the // destination clock domain. The minimum gap between each pulse transfer must be // at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured // between the falling edge of a src_pulse to the rising edge of the next // src_pulse. This minimum gap will guarantee that each rising edge of src_pulse // will generate a pulse the size of one dest_clk period in the destination // clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while // src_rst and/or dest_rst are asserted. .src_rst () // 1-bit input: optional; required when RST_USED = 1 ); endmodule