`timescale 10ns / 10ns // * Micro7020 module system_top ( // rx data input ad9361_rx_clk, // ad9361 receive data clock output input ad9361_rx_frame, // ad9361 receive data frame output signal, indicates I & Q input [11:0] ad9361_rx_data, // ad9361 receive data // tx data output ad9361_tx_clk, // ad9361 feedback clock output ad9361_tx_frame, // ad9361 transmit data frame input signal, indicates I & Q output [11:0] ad9361_tx_data, // ad9361 transmit data // spi interface input ad9361_spi_miso, output ad9361_spi_csn, output ad9361_spi_clk, output ad9361_spi_mosi, // control signal output ad9361_reset_b, // asynchronous reset, active low output ad9361_en_agc, // enable AGC, active high output ad9361_enable, // enable ad9361, active high output ad9361_txnrx, // logic low selects the RX, logic high selects the TX output wire [ 3:0] ad9361_ctrl_in, // ad9361 control in pins, for fastlock control // fixed-io inout fixed_io_ddr_vrn, inout fixed_io_ddr_vrp, inout [53:0] fixed_io_mio, inout fixed_io_ps_clk, inout fixed_io_ps_porb, inout fixed_io_ps_srstb, // clock signal input clk_crystal, // ddr inout [14:0] ddr_addr, inout [ 2:0] ddr_ba, inout ddr_cas_n, inout ddr_ck_n, inout ddr_ck_p, inout ddr_cke, inout ddr_cs_n, inout [ 3:0] ddr_dm, inout [31:0] ddr_dq, inout [ 3:0] ddr_dqs_n, inout [ 3:0] ddr_dqs_p, inout ddr_odt, inout ddr_ras_n, inout ddr_reset_n, inout ddr_we_n, // uart input uart_rx, output uart_tx, // RF interface control signals output wire [ 5:0] rf_gpio, output wire led_red, output wire led_yellow, output wire led_blue ); // ******** Wire & Reg ******** // power on clock domain wire clk_poweron; (*max_fanout = 256 *) wire rst_sys; wire poweron_locked; // ad9361 clock domain wire locked; wire clk_1x; wire clk_2x; wire clk_4x; // emio wire [31:0] gpio_i; wire [31:0] gpio_o; wire [31:0] gpio_t; // enc signal wire enc_fifo_rd_en; wire [31:0] enc_fifo_dout_map; wire enc_fifo_empty; // tx bus wire clk_tx_data_src; wire [31:0] tx_data_src_count; wire [31:0] tx_data_src_tdata; wire tx_data_src_tready; wire tx_data_src_tvalid; // tx signal wire tx_test_flag; // baseband signal wire [11:0] ad9361_rx_data_i; wire [11:0] ad9361_rx_data_q; wire ad9361_rx_frame_i; wire ad9361_rx_frame_q; wire [11:0] ad9361_tx_data_i; wire [11:0] ad9361_tx_data_q; wire [ 2:0] speed_mode; // phy control signal wire phy_rst_vio; wire phy_rst_ps; wire phy_rst; wire phy_tx_test_flag_vio; wire phy_tx_test_flag; // tx signal wire frame_sync_pulse; // ******** Assingment ******** assign ad9361_tx_clk = clk_1x; assign rst_sys = ~poweron_locked; // ad9361 control assign ad9361_enable = gpio_o[0]; // ad9361 enable state machine control assign ad9361_en_agc = gpio_o[1]; // ad9361 agc control assign ad9361_reset_b = gpio_o[2]; // ad9361 reset assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx // ******** Logic Block ******** // ******** Inst ******** clk_wiz_poweron u_clk_wiz_poweron ( // Clock out ports .clk_poweron(clk_poweron), // output clk_poweron // Status and control signals .locked (poweron_locked), // output locked // Clock in ports .clk_crystal(clk_crystal) // input clk_crystal ); // clock domain - ad9361 rx & tx clk_wiz_baseband u_clk_wiz_baseband ( // Clock out ports .clk_1x (clk_1x), // output clk_1x .clk_2x (clk_2x), // output clk_2x .clk_4x (clk_4x), // output clk_4x // Status and control signals .locked (locked), // output locked // Clock in ports .clk_src(ad9361_rx_clk) // input clk_src ); MM7020_BD_wrapper u_MM7020_BD_wrapper ( .ad9361_spi_clk (ad9361_spi_clk), .ad9361_spi_csn (ad9361_spi_csn), .ad9361_spi_miso (ad9361_spi_miso), .ad9361_spi_mosi (ad9361_spi_mosi), .clk_ps (clk_poweron), .rst_ps (rst_sys), // ddr .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), .ddr_cas_n (ddr_cas_n), .ddr_ck_n (ddr_ck_n), .ddr_ck_p (ddr_ck_p), .ddr_cke (ddr_cke), .ddr_cs_n (ddr_cs_n), .ddr_dm (ddr_dm), .ddr_dq (ddr_dq), .ddr_dqs_n (ddr_dqs_n), .ddr_dqs_p (ddr_dqs_p), .ddr_odt (ddr_odt), .ddr_ras_n (ddr_ras_n), .ddr_reset_n (ddr_reset_n), .ddr_we_n (ddr_we_n), // fixed io .fixed_io_ddr_vrn (fixed_io_ddr_vrn), .fixed_io_ddr_vrp (fixed_io_ddr_vrp), .fixed_io_mio (fixed_io_mio), .fixed_io_ps_clk (fixed_io_ps_clk), .fixed_io_ps_porb (fixed_io_ps_porb), .fixed_io_ps_srstb (fixed_io_ps_srstb), // gpio ps .gpio_i (gpio_i), .gpio_o (gpio_o), .gpio_t (gpio_t), // intr pl to ps .pl2ps_intr2 (intr_2ps), .pl2ps_intr3 (pl2ps_intr3), // tx fifo .tx_data_src_count (tx_data_src_count), .tx_data_src_tdata (tx_data_src_tdata), .tx_data_src_tready(tx_data_src_tready), .tx_data_src_tvalid(tx_data_src_tvalid), //phy control signal .phy_rst (phy_rst_ps), .phy_tx_test_flag (phy_tx_test_flag), // uart .uart_rx (uart_rx), .uart_tx (uart_tx) ); // ---- PHY layer logic start // enc_control u_enc_control ( // .clk (clk_poweron), // .rst (rst_sys | phy_rst_ps), // .s_axis_fifo_tvalid (tx_data_src_tvalid), // .s_axis_fifo_tready (tx_data_src_tready), // .s_axis_fifo_tdata (tx_data_src_tdata), // .data_src_count (tx_data_src_count), // .fifo_enc_out_rd_clk (clk_1x), // .fifo_enc_out_rd_en (enc_fifo_rd_en), // .fifo_enc_out_dout_map(enc_fifo_dout_map), // .fifo_enc_out_empty (enc_fifo_empty) // ); // tdma #( // .SLOT_LEN (1250000), // 50MHz--> 25ms // .TIC_TO_PS_LEN (1200000), // .TIC_FRAME_SYNC(42272) // ) u_tdma ( // .clk (clk_1x), // .rst (rst_sys), // .flag_is_master (1'b0), // .flag_frame_sync(frame_sync_pulse), // .intr_2ps (intr_2ps), // .tx_start (tx_start) // ); // Transmitter u_Transmitter ( // .clk (clk_1x), // .rst (rst_sys | phy_rst | phy_rst_vio), // .speed_mode (speed_mode), // .send_data_ready (send_data_ready), // .send_start (send_start), // .send_over (send_over), // .clk_data_src (clk_data_src), // .tx_data_src_tdata (enc_fifo_dout_map), // .tx_data_src_tready(enc_fifo_rd_en), // .tx_data_src_tvalid(~enc_fifo_empty), // .hopping_freq (), // .ad9361_tx_data_i (ad9361_tx_data_i), // .ad9361_tx_data_q (ad9361_tx_data_q), // .test (tx_test_flag | phy_tx_test_flag_vio), // .hop_wait (100) // ); // Receiver u_Receiver ( // .clk (clk_1x), // .clk_2x (clk_2x), // .clk_4x (clk_4x), // .rst (rst_sys | phy_rst | phy_rst_vio), // .speed_mode (speed_mode), // .ad9361_rx_data_i(ad9361_rx_data_i), // .ad9361_rx_data_q(ad9361_rx_data_q), // .frame_sync_pulse(frame_sync_pulse) // ); ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl ( .clk (clk_1x), .rst (rst_sys | phy_rst), .rx_data_i (ad9361_rx_data_i), .rx_data_q (ad9361_rx_data_q), .ad9361_ctrl_in(ad9361_ctrl_in) ); // ---- PHY layer logic end // ad9361 digital port - 1R1T, Dual Port, DDR ad9361_dp_fdd_1r1t ad9361_dp_fdd_1r1t_inst ( // Receive .rx_clk (ad9361_rx_clk), .rx_data (ad9361_rx_data), .rx_frame (ad9361_rx_frame), .rx_data_i (ad9361_rx_data_i), .rx_data_q (ad9361_rx_data_q), .rx_frame_i(ad9361_rx_frame_i), .rx_frame_q(ad9361_rx_frame_q), // Transmit .tx_clk (ad9361_tx_clk), .tx_data_i (ad9361_tx_data_i), .tx_data_q (ad9361_tx_data_q), .tx_data (ad9361_tx_data), .tx_frame (ad9361_tx_frame) ); // ******** CDC ******** xpm_cdc_single #( .DEST_SYNC_FF (4), // DECIMAL; range: 2-10 .INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values .SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages .SRC_INPUT_REG (1) // DECIMAL; 0=do not register input, 1=register input ) xpm_cdc_single_tx_test_flag_ps_inst ( .dest_out(tx_test_flag), // 1-bit output: src_in synchronized to the destination clock domain. This output is registered. .dest_clk(clk_1x), // 1-bit input: Clock signal for the destination clock domain. .src_clk (clk_poweron), // 1-bit input: optional; required when SRC_INPUT_REG = 1 .src_in (phy_tx_test_flag) // 1-bit input: Input signal to be synchronized to dest_clk domain. ); xpm_cdc_sync_rst #( .DEST_SYNC_FF (4), // DECIMAL; range: 2-10 .INIT (1), // DECIMAL; 0=initialize synchronization registers to 0, 1=initialize synchronization registers to 1 .INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values .SIM_ASSERT_CHK(0) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages ) xpm_cdc_sync_rst_phy_rst_inst ( .dest_rst(phy_rst), // 1-bit output: src_rst synchronized to the destination clock domain. This output is registered. .dest_clk(clk_1x), // 1-bit input: Destination clock. .src_rst (phy_rst_ps) // 1-bit input: Source reset signal. ); // ******** Debug ******** ila_ad9361_rx u_ila_ad9361_rx ( .clk (ad9361_rx_clk), .probe0(ad9361_rx_data_i), .probe1(ad9361_rx_data_q), .probe2(u_ad9361_mgc_pin_ctrl.flag_adjust) ); ila_ad9361_tx u_ila_ad9361_tx ( .clk (ad9361_tx_clk), // input wire clk .probe0(ad9361_tx_data_i), // input wire [11:0] probe0 .probe1(ad9361_tx_data_q) // input wire [11:0] probe1 ); vio_phy_control u_vio_phy_control ( .clk (clk_1x), // input wire clk .probe_out0(phy_rst_vio), // output wire [0 : 0] probe_out0 .probe_out1(phy_tx_test_flag_vio), // output wire [0 : 0] probe_out1 .probe_out2(send_start) // output wire [0 : 0] probe_out2 ); vio_gpio u_vio_gpio ( .clk (clk_poweron), .probe_out0(rf_gpio), .probe_out1(led_red), .probe_out2(led_yellow), .probe_out3(led_blue) ); vio_tx_speed_mode u_vio_tx_speed_mode ( .clk (clk_1x), .probe_out0(speed_mode) ); endmodule