`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/08/03 14:53:56
// Design Name: 
// Module Name: trunc_25to12_2dly
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module trunc_25to12_2dly(
	clk,
	din_nd,
	din,
	ctrl,
	dout_nd,
	dout,
	ovrflw
    );
	//--------------------- IN/OUT ------------------------
	input clk;
	input din_nd;
	input [24:0] din;
	input ctrl;
	output reg dout_nd = 0;
	output reg [11:0] dout = 0;
	output reg ovrflw = 0;
	
	//---------------------- delay -----------------------
	reg [24:0] din_dly = 0;
	always @(posedge clk)
			din_dly <= din;
	
	reg sign_bit = 0;
	always @(posedge clk)
			sign_bit <= din[24];
	
	//---------------------- flag -------------------------
	reg signbit3 = 0;
	always @(posedge clk)
		if(din[24:22] == 3'b000 || din[24:22] == 3'b111)
			signbit3 <= 1'b1;
		else 
			signbit3 <= 1'b0;
			
	//------------------------------------------------------
	always @(posedge clk)
		if(signbit3 == 1'b1)
			begin 
			dout <= din_dly[22:11];
			ovrflw <= 0;
			end
		else 
			begin 
			dout <= {sign_bit,{10{!sign_bit}}};
			ovrflw <= 1;
			end 
	reg din_nd_d1 = 0;
	always @(posedge clk) begin
		din_nd_d1 <= din_nd;
		dout_nd <= din_nd_d1;
		end
endmodule