`timescale 1ns / 1ns
// * Engineer: 
// * *************************************************** *
// * ███████╗ ██████╗ ██████╗  ██████╗  ██████╗ ██╗  ██╗ *
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// * ╚══════╝ ╚═════╝ ╚═╝  ╚═╝ ╚═════╝  ╚═════╝ ╚═╝  ╚═╝ *
// * *************************************************** *
// * Create Date: 2024/04/08
// * Update Date: 2024/05/17

// ! PLEASE MAKE SURE THE PARAMETER ARE VALID 
// ! WHEN U INSTANTIATE THIS MODULE
module tdma #(
    // parameter TIC_FRAME_SYNC = 44392
    parameter TIC_FRAME_SYNC = 177568
) (
    input              clk,
    input              rst,
    input              flag_is_master,
    input              flag_frame_sync,
    input  wire [23:0] tdma_slot_len,
    input  wire [23:0] tdma_tic_2_ps,
    output             intr_2ps,
    output             tx_start,
    output reg         rx_rst
);

    // TODO: 需要检查综合后电路是否会被优化
    // BUG: 需要修复bug，重构代码，把主从分开写，通过参数进行优化

    // ******** Wire & Reg  ********

    reg        flag_is_tx_slot;
    reg [23:0] cnt;

    // ******** Assingment  ********

    assign tx_start = flag_is_master & (cnt == 16'd10);
    assign intr_2ps = flag_is_master & (cnt == tdma_tic_2_ps - 1);

    // ******** Logic Block ********



    always @(posedge clk) begin
        if (rst) begin
            cnt <= 0;
        end
        else begin
            if (!flag_is_master && flag_frame_sync) begin
                // slave update cnt
                cnt <= TIC_FRAME_SYNC;
            end
            else begin
                // master
                if (cnt < tdma_slot_len - 1) begin
                    cnt <= cnt + 1;
                end
                else begin
                    cnt <= 0;
                end
            end
        end
    end


    always @(posedge clk) begin
        if (flag_is_master) begin
            rx_rst <= 1;
        end
        else begin
            rx_rst <= flag_is_master | (cnt <= 16'd4);
        end
    end

    // ********    Inst     ********

    // ********    Debug    ********

    vio_tdma u_vio_tdma (
        .clk      (clk),
        .probe_in0(tdma_slot_len),
        .probe_in1(tdma_tic_2_ps),
        .probe_in2(flag_is_master)
    );

    ila_mac_layer u_ila_mac_layer (
        .clk   (clk),
        .probe0(cnt),             // width: 24
        .probe1(tx_start),        // width: 1
        .probe2(rx_rst),          // width: 1
        .probe3(flag_is_master),  // width: 1
        .probe4(intr_2ps),        // width: 1
        .probe5(flag_frame_sync)  // width: 1
    );


endmodule