`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 2019/12/20 21:52:37 // Design Name: // Module Name: SCFDE_recv_FrameSync // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module SCFDE_recv_FrameSync ( input clk, input rst, input rst_ready, input [9:0] datain_i, input [9:0] datain_q, input debug_loss, output reg [9:0] Sync_i = 10'd0, output reg [9:0] Sync_q = 10'd0, output reg Sync_rdy = 1'b0, //判断出峰的标志位，出峰后拉高1clk output reg Pilot_rdy = 1'b0, //出峰后88个clk后拉高1clk，对齐导频头 output reg flag_sync = 1'b0, output reg Pilot_rdy_hide1_d1 = 1'b0 //debug ); //----------卷积与流水累加替代模块----------// //wire [19:0] add_regi_2048; //wire [19:0] add_regq_2048; wire [18:0] add_regi_19bit; wire [18:0] add_regq_19bit; /*conv_add conv_add( .clk(clk), .rst(rst), .data_i(datain_i), .data_q(datain_q), .add_regi_2048(add_regi_2048), .add_regq_2048(add_regq_2048) );*/ wire [ 9:0] dataout_i; wire dout_valid_i; DMF DMF_i ( .clk (clk), .rst (rst), .din_data (datain_i), .din_valid (1'b1), .dout_dmf (add_regi_19bit), .dout_data (dataout_i), .dout_valid(dout_valid_i) ); wire [9:0] dataout_q; wire dout_valid_q; DMF DMF_q ( .clk (clk), .rst (rst), .din_data (datain_q), .din_valid (1'b1), .dout_dmf (add_regq_19bit), .dout_data (dataout_q), .dout_valid(dout_valid_q) ); //----------将实部和虚部的相关结果求近似模值----------// //----------6 delay----------// wire [19:0] reg_add11; wire [18:0] add_regi; wire [18:0] add_regq; wire ApproxAbs_rdy; assign add_regi = (add_regi_19bit[18] == 1'd1) ? -add_regi_19bit : add_regi_19bit; assign add_regq = (add_regq_19bit[18] == 1'd1) ? -add_regq_19bit : add_regq_19bit; ApproxAbs_v2_20bit ApproxAbs_v2_tsync4 ( .clk (clk), .ND (dout_valid_i), .Din_I(add_regi), .Din_Q(add_regq), .Dout (reg_add11), .Rdy (ApproxAbs_rdy) ); //----------将1024个相关结果流水累加----------// reg rst_1 = 1'b0; reg [7:0] rst_1_cnt = 8'b0; always @(posedge clk) begin if (!ApproxAbs_rdy) begin rst_1_cnt = 8'b0; end else begin rst_1_cnt <= rst_1_cnt > 8'd128 ? 8'd129 : rst_1_cnt + 8'd1; end rst_1 <= (rst_1_cnt < 8'd128); end wire [19:0] average_add10; average_1024 average_1024 ( .clk (clk), .rst (rst_1), .nd (ApproxAbs_rdy), .din (reg_add11), .average(average_add10) ); //----------将和求平均值，从而得到门限----------// reg [19:0] reg_save1024 = 20'd0; reg [19:0] reg_save1024_d1 = 20'd0; reg [19:0] reg_save1024_d2 = 20'd0; reg [19:0] reg_save1024_d2_x2 = 20'd0; reg [19:0] reg_save_pilot; reg [19:0] Threshold; reg [ 3:0] th_control = 4'd8; always @(posedge clk) begin if (rst) begin reg_save1024 <= 20'd0; reg_save1024_d1 <= 20'd0; reg_save1024_d2 <= 20'd0; reg_save1024_d2_x2 <= 20'd0; Threshold <= 20'd0; end else begin reg_save1024 <= reg_add11; reg_save1024_d1 <= reg_save1024; reg_save1024_d2 <= reg_save1024_d1; case (th_control) 4'd1: begin Threshold <= average_add10; reg_save1024_d2_x2 <= reg_save1024_d1; end 4'd2: begin Threshold <= {average_add10[18:0], 1'b0}; reg_save1024_d2_x2 <= reg_save1024_d1; end 4'd3: begin Threshold <= average_add10 + {average_add10[18:0], 1'b0}; reg_save1024_d2_x2 <= reg_save1024_d1; end 4'd4: begin Threshold <= {average_add10[17:0], 2'b00}; reg_save1024_d2_x2 <= {reg_save1024_d1[18:0], 1'b0}; end 4'd5: begin Threshold <= average_add10 + {average_add10[17:0], 2'b00}; reg_save1024_d2_x2 <= {reg_save1024_d1[18:0], 1'b0}; end 4'd6: begin Threshold <= {average_add10[18:0], 1'b0} + {average_add10[17:0], 2'b00}; reg_save1024_d2_x2 <= reg_save1024_d1 + {reg_save1024_d1[18:0], 1'b0}; end 4'd7: begin Threshold <= average_add10 + {average_add10[18:0], 1'b0} + {average_add10[17:0], 2'b0}; reg_save1024_d2_x2 <= reg_save1024_d1 + {reg_save1024_d1[18:0], 1'b0}; end 4'd8: begin Threshold <= {average_add10[16:0], 3'b000}; reg_save1024_d2_x2 <= {reg_save1024_d1[17:0], 2'b00}; end 4'd9: begin Threshold <= average_add10 + {average_add10[16:0], 3'b000}; reg_save1024_d2_x2 <= {reg_save1024_d1[17:0], 2'b00}; end default: begin Threshold <= {average_add10[17:0], 2'b00}; reg_save1024_d2_x2 <= {reg_save1024_d1[18:0], 1'b0}; end endcase end end //----------将相关求和后的近似模值与门限比较；若高于门限，再与相邻近似模值比较----------// reg [ 6:0] counter88 = 7'd0; //rst之后500个clk之内不允许拉高Pilot_rdy_hide1 reg [11:0] count_rst500 = 12'd0; reg [ 3:0] state_framesync; always @(posedge clk) begin if (rst) begin count_rst500 <= 15'd0; state_framesync <= 4'd0; counter88 <= 7'd0; reg_save_pilot <= 20'd0; Pilot_rdy_hide1_d1 <= 1'b0; flag_sync <= 1'b0; Sync_rdy <= 1'b0; end else begin case (state_framesync) 4'd0: begin if (count_rst500 == 12'd32) begin //等待32个clk的rst count_rst500 <= 12'd0; state_framesync <= 4'd1; end else begin count_rst500 <= count_rst500 + 12'd1; state_framesync <= state_framesync; end end 4'd1: begin if (Threshold != 20'd0) begin state_framesync <= 4'd2; end else begin state_framesync <= state_framesync; end end 4'd2: begin if (count_rst500 == 12'd2048) begin //等待计数过2048个clk count_rst500 <= 12'd0; state_framesync <= 4'd3; end else begin count_rst500 <= count_rst500 + 12'd1; state_framesync <= state_framesync; end end 4'd3: begin if ((reg_save1024_d1 > Threshold)) begin //检测到过门限值 if ((reg_save1024_d1 >= reg_save1024) && (reg_save1024_d1 >= reg_save1024_d2)) begin if (reg_save1024_d1 >= 20'd128) begin Sync_rdy <= 1'b1; state_framesync <= 4'd4; reg_save_pilot <= reg_save1024_d1; end else begin Sync_rdy <= 1'b0; state_framesync <= state_framesync; end end else begin Sync_rdy <= 1'b0; end end else begin Sync_rdy <= 1'b0; end end 4'd4: begin if (counter88 == 7'd86) begin Sync_rdy <= 1'b0; flag_sync <= 1'b1; Pilot_rdy_hide1_d1 <= 1'b1; state_framesync <= 4'd5; end else if (counter88 >= 7'd32) begin if (reg_save_pilot >= reg_save1024_d2_x2) begin // ? reg_save_pilot是DMF滤波器输出峰值 counter88 <= counter88 + 7'd1; end else begin counter88 <= 7'd0; state_framesync <= 4'd3; Sync_rdy <= 1'b0; end flag_sync <= 1'b0; end else begin counter88 <= counter88 + 7'd1; flag_sync <= 1'b0; end end 4'd5: begin flag_sync <= 1'b1; Pilot_rdy_hide1_d1 <= 1'b0; state_framesync <= state_framesync; end default: begin if (count_rst500 == 12'd32) begin count_rst500 <= 12'd0; state_framesync <= 4'd1; end else begin count_rst500 <= count_rst500 + 12'd1; state_framesync <= state_framesync; end end endcase end end //----------将输入数据打延迟，与Sync_rdy拉高的时刻同步输出----------// reg [9:0] datain_i_d1; reg [9:0] datain_q_d1; reg [9:0] datain_i_d2; reg [9:0] datain_q_d2; reg [9:0] datain_i_d3; reg [9:0] datain_q_d3; reg [9:0] datain_i_d4; reg [9:0] datain_q_d4; reg [9:0] datain_i_d5; reg [9:0] datain_q_d5; reg [9:0] datain_i_d6; reg [9:0] datain_q_d6; reg [9:0] datain_i_d7; reg [9:0] datain_q_d7; reg [9:0] datain_i_d8; reg [9:0] datain_q_d8; reg [9:0] datain_i_d9; reg [9:0] datain_q_d9; /*shift_ram_x shift_ram_i1 ( .D(datain_i), .CLK(clk), .Q(datain_i_d3) ); wire [9:0] datain_q_d3; shift_ram_x shift_ram_q1 ( .D(datain_q), .CLK(clk), .Q(datain_q_d3) );*/ always @(posedge clk) begin if (rst) begin Sync_i <= 10'd0; Sync_q <= 10'd0; datain_i_d1 <= 10'd0; datain_q_d1 <= 10'd0; datain_i_d2 <= 10'd0; datain_q_d2 <= 10'd0; datain_i_d3 <= 10'd0; datain_q_d3 <= 10'd0; datain_i_d4 <= 10'd0; datain_q_d4 <= 10'd0; datain_i_d5 <= 10'd0; datain_q_d5 <= 10'd0; datain_i_d6 <= 10'd0; datain_q_d6 <= 10'd0; datain_i_d7 <= 10'd0; datain_q_d7 <= 10'd0; datain_i_d8 <= 10'd0; datain_q_d8 <= 10'd0; datain_i_d9 <= 10'd0; datain_q_d9 <= 10'd0; end else begin datain_i_d1 <= datain_i; datain_q_d1 <= datain_q; datain_i_d2 <= datain_i_d1; datain_q_d2 <= datain_q_d1; datain_i_d3 <= datain_i_d2; datain_q_d3 <= datain_q_d2; datain_i_d4 <= datain_i_d3; datain_q_d4 <= datain_q_d3; datain_i_d5 <= datain_i_d4; datain_q_d5 <= datain_q_d4; datain_i_d6 <= datain_i_d5; datain_q_d6 <= datain_q_d5; datain_i_d7 <= datain_i_d6; datain_q_d7 <= datain_q_d6; datain_i_d8 <= datain_i_d7; datain_q_d8 <= datain_q_d7; datain_i_d9 <= datain_i_d8; datain_q_d9 <= datain_q_d8; Sync_i <= datain_i_d9; Sync_q <= datain_q_d9; end end // `ifdef FrameSync_debug /* ila_FS_inst ila_FS_inst( .clk(clk), .probe0(datain_i),//10 .probe1(datain_q),//10 .probe2(rst),//1 .probe3(Pilot_rdy_hide1_d1),//1 .probe4(reg_save1024_d2_x2),//20 .probe5(average_add10),//20 .probe6(Threshold),//20 .probe7(reg_save1024_d1),//20 .probe8(debug_loss),//1 .probe9(flag_sync),//1 .probe10(state_framesync),//4 .probe11(counter88),//7 .probe12(Sync_rdy),//1 .probe13(th_control)//4 );*/ // ILA LARGE /*ila_large ila_MF_large_inst( .clk(clk), .probe0(datain_i[9:0]), .probe1({rst_ready,rst,Pilot_rdy_hide1}) );*/ // `endif endmodule