`timescale 10ns / 10ns // * Micro7020 module system_top ( // rx data input ad9361_rx_clk, // ad9361 receive data clock output input ad9361_rx_frame, // ad9361 receive data frame output signal, indicates I & Q input [11:0] ad9361_rx_data, // ad9361 receive data // tx data output ad9361_tx_clk, // ad9361 feedback clock output ad9361_tx_frame, // ad9361 transmit data frame input signal, indicates I & Q output [11:0] ad9361_tx_data, // ad9361 transmit data // spi interface input ad9361_spi_miso, output ad9361_spi_csn, output ad9361_spi_clk, output ad9361_spi_mosi, // control signal output ad9361_reset_b, // asynchronous reset, active low output ad9361_en_agc, // enable AGC, active high output ad9361_enable, // enable ad9361, active high output ad9361_txnrx, // logic low selects the RX, logic high selects the TX output wire [ 3:0] ad9361_ctrl_in, // ad9361 control in pins, for fastlock control // fixed-io inout fixed_io_ddr_vrn, inout fixed_io_ddr_vrp, inout [53:0] fixed_io_mio, inout fixed_io_ps_clk, inout fixed_io_ps_porb, inout fixed_io_ps_srstb, // clock signal input clk_crystal, // ddr inout [14:0] ddr_addr, inout [ 2:0] ddr_ba, inout ddr_cas_n, inout ddr_ck_n, inout ddr_ck_p, inout ddr_cke, inout ddr_cs_n, inout [ 3:0] ddr_dm, inout [31:0] ddr_dq, inout [ 3:0] ddr_dqs_n, inout [ 3:0] ddr_dqs_p, inout ddr_odt, inout ddr_ras_n, inout ddr_reset_n, inout ddr_we_n, // uart input uart_rx, output uart_tx, // RF interface control signals output wire [ 5:0] rf_gpio, output wire led_red, output wire led_yellow, output wire led_blue ); // ******** Wire & Reg ******** // power on clock domain wire clk_poweron; (*max_fanout = 256 *) wire rst_sys; wire poweron_locked; // ad9361 clock domain wire locked; wire clk_1x; wire clk_2x; wire clk_4x; wire clk_quarter; wire clk_half; // emio wire [31:0] gpio_i; wire [31:0] gpio_o; wire [31:0] gpio_t; // enc signal wire enc_fifo_rd_en; wire [31:0] enc_fifo_dout_map; wire enc_fifo_empty; // tx bus wire clk_tx_data_src; wire [31:0] tx_data_src_count; wire [31:0] tx_data_src_tdata; wire tx_data_src_tready; wire tx_data_src_tvalid; // tx signal wire tx_test_flag; wire flag_mgc_done_pulse; // rx bus wire [31:0] rx_data_src_fifo_tdata; wire rx_data_src_fifo_tlast; wire rx_data_src_fifo_tready; wire rx_data_src_fifo_tvalid; // baseband signal wire [11:0] ad9361_rx_data_i; wire [11:0] ad9361_rx_data_q; wire ad9361_rx_frame_i; wire ad9361_rx_frame_q; wire [11:0] ad9361_tx_data_i; wire [11:0] ad9361_tx_data_q; wire [ 2:0] speed_mode; // mux wire bb_tx_iq_reverse; wire bb_rx_iq_reverse; wire [11:0] bb_tx_i; wire [11:0] bb_tx_q; wire [11:0] bb_rx_i; wire [11:0] bb_rx_q; // phy control signal wire phy_rst_vio; wire phy_rst; wire phy_tx_test_flag_vio; wire phy_tx_test_flag; wire phy_tx_iq_reverse; wire phy_rx_iq_reverse; wire tdma_flag_is_master; wire [31:0] tdma_slot_len; wire [31:0] tdma_tic_2_ps; wire [31:0] tdma_id_cfg; wire tdma_recv_cur_slot_id_valid; wire [ 7:0] tdma_recv_cur_slot_id; // tx signal wire frame_sync_pulse; wire rx_rst; wire tx_done; wire intr_2ps_vio; reg intr_2ps_vio_d1; wire intr_2ps_vio_pos; wire tx_start_vio; reg tx_start_vio_d1; wire tx_start_vio_pos; // rx wire rx_err_flag_pos; // vio wire rst_manual; wire rx_rst_vio; wire [ 7:0] node_id; wire intr_2ps; wire [ 7:0] max_slot_num; // ******** Assingment ******** assign ad9361_tx_clk = clk_1x; assign rst_sys = ~poweron_locked; // ad9361 control assign ad9361_enable = gpio_o[0]; // ad9361 enable state machine control assign ad9361_en_agc = gpio_o[1]; // ad9361 agc control assign ad9361_reset_b = gpio_o[2]; // ad9361 reset assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx assign ad9361_tx_data_i = phy_tx_iq_reverse ? bb_tx_q : bb_tx_i; assign ad9361_tx_data_q = phy_tx_iq_reverse ? bb_tx_i : bb_tx_q; assign bb_rx_i = phy_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i; assign bb_rx_q = phy_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q; // ******** Logic Block ******** // ******** Inst ******** clk_wiz_poweron u_clk_wiz_poweron ( // Clock out ports .clk_poweron(clk_poweron), // output clk_poweron // Status and control signals .locked (poweron_locked), // output locked // Clock in ports .clk_crystal(clk_crystal) // input clk_crystal ); // clock domain - ad9361 rx & tx clk_wiz_baseband u_clk_wiz_baseband ( // Clock out ports .clk_1x (clk_1x), // output clk_1x .clk_2x (clk_2x), // output clk_2x .clk_4x (clk_4x), // output clk_4x .clk_quarter(clk_quarter), .clk_half (clk_half), // Status and control signals .locked (locked), // output locked // Clock in ports .clk_src (ad9361_rx_clk) // input clk_src ); MM7020_BD_wrapper u_MM7020_BD_wrapper ( .ad9361_spi_clk (ad9361_spi_clk), .ad9361_spi_csn (ad9361_spi_csn), .ad9361_spi_miso (ad9361_spi_miso), .ad9361_spi_mosi (ad9361_spi_mosi), .clk_ps (clk_poweron), .rst_ps (rst_sys), // ddr .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), .ddr_cas_n (ddr_cas_n), .ddr_ck_n (ddr_ck_n), .ddr_ck_p (ddr_ck_p), .ddr_cke (ddr_cke), .ddr_cs_n (ddr_cs_n), .ddr_dm (ddr_dm), .ddr_dq (ddr_dq), .ddr_dqs_n (ddr_dqs_n), .ddr_dqs_p (ddr_dqs_p), .ddr_odt (ddr_odt), .ddr_ras_n (ddr_ras_n), .ddr_reset_n (ddr_reset_n), .ddr_we_n (ddr_we_n), // fixed io .fixed_io_ddr_vrn (fixed_io_ddr_vrn), .fixed_io_ddr_vrp (fixed_io_ddr_vrp), .fixed_io_mio (fixed_io_mio), .fixed_io_ps_clk (fixed_io_ps_clk), .fixed_io_ps_porb (fixed_io_ps_porb), .fixed_io_ps_srstb (fixed_io_ps_srstb), // gpio ps .gpio_i (gpio_i), .gpio_o (gpio_o), .gpio_t (gpio_t), // intr pl to ps .pl_tx_intr (intr_2ps), .pl_rx_intr (rx_data_src_fifo_tlast), .pl_intr0 (rx_err_flag_pos), // tx fifo .tx_data_src_count (tx_data_src_count), .tx_data_src_tdata (tx_data_src_tdata), .tx_data_src_tready (tx_data_src_tready), .tx_data_src_tvalid (tx_data_src_tvalid), // rx fifo .clk_rx_data_src_fifo (clk_half), .rst_rx_data_src_fifo (rx_rst), .rx_data_src_fifo_tdata (rx_data_src_fifo_tdata), .rx_data_src_fifo_tlast (rx_data_src_fifo_tlast), .rx_data_src_fifo_tready (rx_data_src_fifo_tready), .rx_data_src_fifo_tvalid (rx_data_src_fifo_tvalid), // phy clock and rst to ps .clk_phy (clk_1x), .rst_phy_n (~rst_sys), // phy control signal .phy_rst (phy_rst), .phy_tx_test_flag (phy_tx_test_flag), .phy_tx_iq_reverse (phy_tx_iq_reverse), .phy_rx_iq_reverse (phy_rx_iq_reverse), .tdma_flag_is_master (tdma_flag_is_master), .tdma_slot_len (tdma_slot_len), .tdma_tic_2_ps (tdma_tic_2_ps), .tdma_id_cfg (tdma_id_cfg), .tdma_recv_cur_slot_id_valid(tdma_recv_cur_slot_id_valid), .tdma_recv_cur_slot_id (tdma_recv_cur_slot_id), // uart .uart_rx (uart_rx), .uart_tx (uart_tx) ); tdma u_tdma ( .clk (clk_1x), .rst (rst_sys), .flag_frame_sync (frame_sync_pulse), .tdma_slot_len (tdma_slot_len[23:0]), .tdma_tic_2_ps (tdma_tic_2_ps[23:0]), .tdma_slot_num (tdma_id_cfg[15:8]), .local_id (tdma_id_cfg[7:0]), .recevied_cur_slot_id_valid(tdma_recv_cur_slot_id_valid), .recevied_cur_slot_id (tdma_recv_cur_slot_id), .intr_2ps (intr_2ps), .tx_start (tx_start), .rx_rst (rx_rst) ); // ---- PHY layer logic start enc_control u_enc_control ( .clk (clk_poweron), .rst (rst_sys | phy_rst), .s_axis_fifo_tvalid (tx_data_src_tvalid), .s_axis_fifo_tready (tx_data_src_tready), .s_axis_fifo_tdata (tx_data_src_tdata), .data_src_count (tx_data_src_count), .fifo_enc_out_rd_clk (clk_1x), .fifo_enc_out_rd_en (enc_fifo_rd_en), .fifo_enc_out_dout_map(enc_fifo_dout_map), .fifo_enc_out_empty (enc_fifo_empty) ); Transmitter u_Transmitter ( .clk (clk_1x), .rst (rst_sys | phy_rst), .speed_mode (0), .send_data_ready (send_data_ready), .send_start (tx_start), .send_over (tx_done), .clk_data_src (clk_data_src), .tx_data_src_tdata (enc_fifo_dout_map), .tx_data_src_tready(enc_fifo_rd_en), .tx_data_src_tvalid(~enc_fifo_empty), .hopping_freq (), .ad9361_tx_data_i (bb_tx_i), .ad9361_tx_data_q (bb_tx_q), .test (phy_tx_test_flag), .hop_wait (100) ); RecvTop u_RecvTop ( .clk (clk_1x), .clk_2x (clk_2x), .clk_4x (clk_4x), .clk_half (clk_half), .clk_quarter (clk_quarter), .rst (rst_sys | rx_rst | phy_rst), .rst2 (rst_sys | phy_rst), .dini (bb_rx_i), .dinq (bb_rx_q), .ad9361_ctrl_in (ad9361_ctrl_in), .flag_mgc_done_pulse (flag_mgc_done_pulse), .frame_sync_pulse_1x (frame_sync_pulse), .vio_tsync_inter16 (1), .EQUenable_vio (1), .Zerozone_vio (8'd29), .vio_stopbit (7'd60), .flag_stop (flag_stop), .addr_stop (addr_stop), .recvNetData (recvNetData), .recvNetDataNd (recvNetDataNd), .rx_data_src_fifo_tdata (rx_data_src_fifo_tdata), .rx_data_src_fifo_tlast (rx_data_src_fifo_tlast), .rx_data_src_fifo_tready(rx_data_src_fifo_tready), .rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid), .err_flag_pos (rx_err_flag_pos) ); // ---- PHY layer logic end // ad9361 digital port - 1R1T, Dual Port, DDR ad9361_dp_fdd_1r1t ad9361_dp_fdd_1r1t_inst ( // Receive .rx_clk (ad9361_rx_clk), .rx_data (ad9361_rx_data), .rx_frame (ad9361_rx_frame), .rx_data_i (ad9361_rx_data_i), .rx_data_q (ad9361_rx_data_q), .rx_frame_i(ad9361_rx_frame_i), .rx_frame_q(ad9361_rx_frame_q), // Transmit .tx_clk (ad9361_tx_clk), .tx_data_i (ad9361_tx_data_i), .tx_data_q (ad9361_tx_data_q), .tx_data (ad9361_tx_data), .tx_frame (ad9361_tx_frame) ); // ******** CDC ******** // ******** Debug ******** // ila_ad9361_rx u_ila_ad9361_rx ( // .clk (ad9361_rx_clk), // .probe0(ad9361_rx_data_i), // .probe1(ad9361_rx_data_q), // .probe2(u_RecvTop.flag_mgc_done) // ); // ila_ad9361_tx u_ila_ad9361_tx ( // .clk (ad9361_tx_clk), // input wire clk // .probe0(ad9361_tx_data_i), // input wire [11:0] probe0 // .probe1(ad9361_tx_data_q) // input wire [11:0] probe1 // ); endmodule