`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/11/18 21:03:55
// Design Name: 
// Module Name: TSync_Abs_new4
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
//4倍过采样不内插
//帧内不更新

module TSync_Abs_new4(
    input				clk,
	input				rst,
	input			 	framesync_Interpolation,
	output	reg			framesync_out4 = 1'd0,
	
	input		[9:0]	dataini,
	input		[9:0]	datainq,
	
	output	reg			TSyncout_nd = 1'd0,
	output	reg	[9:0]	TSyncout_i = 10'd0,
	output	reg	[9:0]	TSyncout_q = 10'd0,
	
	//debug
	output	reg [1:0] 	cnt = 2'd0,  //12.5
	
	output	reg [1:0] 	flag_clk4 = 2'd0 //12.5

	
	);
	
	//-------------------------------------状态机控制----------------------------------------------//
	
	
	// reg [3:0] cnt = 4'd0;
	reg       nd_1 = 1'd0;
	
	reg       flag_framesync = 1'd0;
	
	// reg [3:0] flag_clk = 4'd0;
	// reg [1:0] flag_num = 2'd0;
	
	
	
	always @(posedge clk)begin
		if(rst)begin
			cnt <= 2'd3;
			nd_1 <= 1'd0;
			
			TSyncout_nd <= 1'd0;
			TSyncout_i  <= 10'd0;
			TSyncout_q  <= 10'd0;
			
			flag_framesync	<= 1'd0;
			framesync_out4	<= 1'd0;
		end
		else begin
			cnt <= cnt + 2'd1;
			
			if(cnt == 2'd3) nd_1 <= 1'd1;
			else			nd_1 <= 1'd0;
				if(framesync_Interpolation) begin
					if(cnt == flag_clk4) begin
						framesync_out4 <= 1'd1;
						TSyncout_nd <= 1'd1;
						TSyncout_i  <= dataini;
						TSyncout_q  <= datainq;
						flag_framesync	<= 1'd0;
					end
					else begin
						framesync_out4 <= 1'd0;
						TSyncout_nd <= 1'd0;
						TSyncout_i  <= 10'd0;
						TSyncout_q  <= 10'd0;
						flag_framesync	<= 1'd1;
					end
				end
				else begin
					framesync_out4 <= 1'd0;
					flag_framesync	<= 1'd0;
					TSyncout_nd <= 1'd0;
					TSyncout_i  <= 10'd0;
					TSyncout_q  <= 10'd0;
				end
			
			// if(cnt == flag_clk4) begin
				// TSyncout_nd <= 1'd1;
				// TSyncout_i  <= dataini;
				// TSyncout_q  <= datainq;
			// end
			// else begin
				// TSyncout_nd <= 1'd0;
			// end

		end
	end
	
	
	//---------------------------------------求近似模值Abs，delay=6-------------------------------------//
	wire [10:0] data_Abs;
	ApproxAbs_v2 ApproxAbs_v2_tsync (
		.clk	(clk), 
		.ND		(1'd1), 
		.Din_I	(dataini), 
		.Din_Q	(datainq), 
		.Dout	(data_Abs), 
		.Rdy	()
    );
	
	
	
	reg nd_2 = 1'd0;
	reg nd_3 = 1'd0;
	reg nd_4 = 1'd0;
	reg nd_5 = 1'd0;
	reg nd_6 = 1'd0;
	reg nd_7 = 1'd0;
	
	always @(posedge clk)begin
		nd_2 <= nd_1;
		nd_3 <= nd_2;
		nd_4 <= nd_3;
		nd_5 <= nd_4;
		
		nd_6 <= nd_5;
		nd_7 <= nd_6;
	end
	
	
	
	//-------------------------------------累加，delay=1-------------------------------------------------//
	reg [19:0] acc_01 = 20'd0;
	reg [19:0] acc_02 = 20'd0;
	reg [19:0] acc_03 = 20'd0;
	reg [19:0] acc_04 = 20'd0;
	
	reg [1:0] cnt_4 =2'd0;
	reg       nd_acc = 1'd0;
	reg nd_flag = 1'd0;
	
	reg flag_cnt_0 = 1'd0;
	
	reg	[5:0]	cnt_64  = 6'd0;
	reg	[6:0]	cnt_128 = 7'd0;
	reg	[7:0]	cnt_256 = 8'd0;
	reg	[8:0]	cnt_512 = 9'd0;
	reg	[9:0]	cnt_1024 = 10'd0;
	
	reg [2:0]	state_tsync4 = 3'd0;
	
	always @(posedge clk)begin
		if(rst)begin
			acc_01 <= 20'd0;
			acc_02 <= 20'd0;
			acc_03 <= 20'd0;
			acc_04 <= 20'd0;
			
			cnt_4 <= 2'd3;
			nd_acc <= 1'd0;
			nd_flag<= 1'd0;
			
			cnt_64  <= 6'd0;
			cnt_128 <= 7'd0;
			cnt_256 <= 8'd0;
			cnt_512 <= 9'd0;
			cnt_1024 <= 10'd0;
			
			flag_cnt_0 <= 1'd0;
			
			state_tsync4 <= 3'd0;
		end
		else begin
			if(nd_6)	cnt_4  <= 4'd0;
			else     	cnt_4  <= cnt_4 + 4'd1;
			
			if (nd_6)	nd_flag <= 1'd1;
			else 		nd_flag <= nd_flag;
			
			case(state_tsync4)
			//等待第一次的数据幅值估计结果（与nd_7对齐）
			3'd0:begin
				if(nd_6)	state_tsync4 <= 3'd1;
				else     	state_tsync4 <= state_tsync4;
			end
			//此clk内nd_7、第一次的数据幅值估计结果同时到来，cnt_4结果为4'd0。
			//累积，直到最后一个累积结束后转至下一状态
			3'd1:begin
				if(cnt_4==2'd3)	begin
					cnt_64		<=cnt_64   +6'd1;
					cnt_128		<=cnt_128  +7'd1;
					cnt_256		<=cnt_256  +8'd1;
					cnt_512		<=cnt_512  +9'd1;
					cnt_1024 	<=cnt_1024 +10'd1;
					
					if(cnt_512==9'd511)	flag_cnt_0 <= 1'd1;
					else				flag_cnt_0 <= 1'd0;
				end
				else begin			
					cnt_64		<= cnt_64;
					cnt_128		<= cnt_128 ;
					cnt_256		<= cnt_256 ;
					cnt_512		<= cnt_512 ;
					cnt_1024 	<= cnt_1024;
					flag_cnt_0	<= 1'd0;
				end
			     
				if(cnt_512==9'd0) begin
					case(cnt_4)        
					2'd0:begin          
						acc_01 <= {9'd0,data_Abs};
						nd_acc <= 1'd0;
					end                
					2'd1:begin         
						acc_02 <= {9'd0,data_Abs};
						nd_acc <= 1'd0;
					end                
					2'd2:begin         
						acc_03 <= {9'd0,data_Abs};
						nd_acc <= 1'd0;
					end                 
					2'd3:begin          
						acc_04 <= {9'd0,data_Abs};
						nd_acc <= 1'd1; 
					end                 
					endcase    
				end
				else begin
					case(cnt_4)        
					2'd0:begin          
						acc_01 <= acc_01 + {9'd0,data_Abs};
						nd_acc <= 1'd0;
					end                
					2'd1:begin         
						acc_02 <= acc_02 + {9'd0,data_Abs};
						nd_acc <= 1'd0;
					end                
					2'd2:begin         
						acc_03 <= acc_03 + {9'd0,data_Abs};
						nd_acc <= 1'd0;
					end                 
					2'd3:begin          
						acc_04 <= acc_04 + {9'd0,data_Abs};
						nd_acc <= 1'd1;
					end                         
					endcase 
				end
				
				if(cnt_512==9'd511&&cnt_4==2'd3)	state_tsync4 <= 3'd2;
				else								state_tsync4 <= state_tsync4;
			end
			3'd2:begin
				state_tsync4	<= state_tsync4;
				flag_cnt_0 		<= 1'd0;
			end
			default:state_tsync4 <= 3'd0;
			endcase
		end
	end
	
	
	
	//---------------------------------------排序找最大值，delay=3-------------------------------------------------//
	
	reg  [19:0] temp_1_01 = 20'd0;
	reg  [19:0] temp_1_02 = 20'd0;

	reg	  [1:0] flag_clk_1_01 =2'd0;
	reg	  [1:0] flag_clk_1_02 =2'd0;
	
	reg			nd_acc1 = 1'd0;
	
	//ila用
	reg [19:0] acc_01_reg = 20'd0;
	reg [19:0] acc_02_reg = 20'd0;
	reg [19:0] acc_03_reg = 20'd0;
	reg [19:0] acc_04_reg = 20'd0;
	
	always @(posedge clk)begin
		if(rst)begin
			temp_1_01 <= 20'd0;
			temp_1_02 <= 20'd0;
			
			flag_clk_1_01 <=2'd0;
			flag_clk_1_02 <=2'd0;

			nd_acc1      <= 1'd0;
			
			//ila用
			acc_01_reg <= 20'd0;
			acc_02_reg <= 20'd0;
			acc_03_reg <= 20'd0;
			acc_04_reg <= 20'd0;
		end
		else begin
			if(nd_acc&&flag_cnt_0) begin
				nd_acc1 <= 1'd1;
				
				//ila用
				acc_01_reg <= acc_01;
				acc_02_reg <= acc_02;
				acc_03_reg <= acc_03;
				acc_04_reg <= acc_04;
				//ila用				
				
				if(acc_01>=acc_02) begin
					temp_1_01	 <= acc_01;
					flag_clk_1_01 <= 2'd0;
				end
				else begin
					temp_1_01	 <= acc_02;
					flag_clk_1_01 <= 2'd1;
				end
				
				if(acc_03>=acc_04) begin
					temp_1_02	 <= acc_03;
					flag_clk_1_02 <= 2'd2;
				end
				else begin
					temp_1_02	 <= acc_04;
					flag_clk_1_02 <= 2'd3;
				end
			end
			else nd_acc1      <= 1'd0;
		end
	end
	
		
	

	//----------------------------------------------------给采样标志,delay=1--------------------------------------//
	
	reg nd_acc2 = 1'd0;
	always @(posedge clk)begin
		if(rst)begin
			flag_clk4 <= 2'd0;		
			nd_acc2  <= 1'd0;
		end
		else begin
			nd_acc2 <= nd_acc1;
			if(nd_acc1) begin
				if(temp_1_01>=temp_1_02) begin
					flag_clk4 <= flag_clk_1_01;
				end
				else begin
					flag_clk4 <= flag_clk_1_02;
				end
			end
		end
	end
	
	
	
	
	//ila用
	// reg [6:0] state_check = 7'd0;
	// always @(posedge clk)begin
		// if(rst)begin
			// state_check		<= 7'd0;
			// flag_TSync_check<= 1'd0;
			// cnt_tsync_shixu	<= 4'd0;
			// flag_tongdao 	<= 1'd0;
			// acc_tsync		<= 20'd0;
			// num_tsync 		<= num_tsync;
		// end
		// else begin
			// case(state_check)
			// 7'd0:begin
				// if(nd_acc4) begin
					// flag_TSync_check<= 1'd0;
					// state_check	<= 7'd1;
				// end
				// else begin
					// flag_TSync_check<= 1'd0;
					// state_check	<= state_check;
				// end
				// cnt_tsync_shixu	<= 4'd0;
				// flag_tongdao 	<= 1'd0;
				// acc_tsync		<= acc_tsync;
				// num_tsync		<= num_tsync;
			// end
			// 7'd1:begin
				// if(flag_save) begin
					// flag_TSync_check<= 1'd0;
					// state_check		<= 7'd2;
				// end
				// else begin
					// flag_TSync_check<= 1'd0;
					// state_check		<= state_check;
				// end
				// cnt_tsync_shixu	<= 4'd1 + cnt_tsync_shixu;
				// flag_tongdao 	<= 1'd0;
				// acc_tsync		<= acc_tsync;
				// num_tsync 		<= num_tsync;
			// end
			// 7'd2:begin
				// if(cnt==2'd3) begin
					// flag_TSync_check<= 1'd1;
					// state_check		<= 7'd3;
				// end
				// else begin
					// flag_TSync_check<= 1'd0;
					// state_check		<= state_check;
				// end
				// cnt_tsync_shixu	<= 4'd1 + cnt_tsync_shixu;
				// flag_tongdao 	<= 1'd0;
				// acc_tsync		<= acc_tsync;
				// num_tsync 		<= num_tsync;
			// end
			// 7'd03:begin acc_tsync <= acc_01_reg; num_tsync <= 6'd00; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd04; end
			// 7'd04:begin acc_tsync <= acc_02_reg; num_tsync <= 6'd01; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd05; end
			// 7'd05:begin acc_tsync <= acc_03_reg; num_tsync <= 6'd02; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd06; end
			// 7'd06:begin acc_tsync <= acc_04_reg; num_tsync <= 6'd03; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd07; end
			// 7'd07:begin acc_tsync <= acc_05_reg; num_tsync <= 6'd04; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd08; end
			// 7'd08:begin acc_tsync <= acc_06_reg; num_tsync <= 6'd05; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd09; end
			// 7'd09:begin acc_tsync <= acc_07_reg; num_tsync <= 6'd06; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd10; end
			// 7'd10:begin acc_tsync <= acc_08_reg; num_tsync <= 6'd07; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd11; end
			// 7'd11:begin acc_tsync <= acc_09_reg; num_tsync <= 6'd08; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd12; end
			// 7'd12:begin acc_tsync <= acc_10_reg; num_tsync <= 6'd09; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd13; end
			// 7'd13:begin acc_tsync <= acc_11_reg; num_tsync <= 6'd10; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd14; end
			// 7'd14:begin acc_tsync <= acc_12_reg; num_tsync <= 6'd11; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd15; end
			// 7'd15:begin acc_tsync <= acc_13_reg; num_tsync <= 6'd12; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd16; end
			// 7'd16:begin acc_tsync <= acc_14_reg; num_tsync <= 6'd13; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd17; end
			// 7'd17:begin acc_tsync <= acc_15_reg; num_tsync <= 6'd14; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd18; end
			// 7'd18:begin acc_tsync <= acc_16_reg; num_tsync <= 6'd15; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd0; end
			// endcase
		// end
	// end
	
	
	
	
	
	
	
	// integer	handle01; 	
	// integer	handle02; 	

	// reg enable = 0;
	// initial begin
      // handle01=$fopen("TSyncout_i.txt","w"); $fclose(handle01);
      // handle02=$fopen("TSyncout_q.txt","w"); $fclose(handle02);

		// #10;
		// enable = 1;
	// end

	// always@(posedge clk)begin
		// if(enable)begin
			// if(TSyncout_nd)begin
				// handle01=$fopen("TSyncout_i.txt","a+");$fwrite(handle01,"%d\n",$signed(TSyncout_i));$fclose(handle01);
				// handle02=$fopen("TSyncout_q.txt","a+");$fwrite(handle02,"%d\n",$signed(TSyncout_q));$fclose(handle02);
			// end
		// end
	// end	
	
	
		

endmodule