`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/11/14 17:44:48
// Design Name: 
// Module Name: FrameMerge
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module FrameMerge(
	input clk,
	input rst,
	input rst2,
	input sync,
	input nd,
	input din,
	
	input [6:0] vio_stopbit,
	
	input				frameIDnd,
	input				clk2,
	output reg			framerdy		= 1'b0,
	// output reg			flag_recvram	= 1'b0,
	// input		[12:0]	recv_addr1,
	// input		[12:0]	recv_addr2,
	// output 		[7:0]	recv_data1,
	// output 		[7:0]	recv_data2,
	input		[13:0]	recv_addr_new_0,
	input		[13:0]	recv_addr_new_1,
	input		[13:0]	recv_addr_new_2,
	input		[13:0]	recv_addr_new_3,
	output 		[7:0]	recv_data_new_0,
	output 		[7:0]	recv_data_new_1,
	output 		[7:0]	recv_data_new_2,
	output 		[7:0]	recv_data_new_3,
	output reg	[16:0]	RAMaddra_write_0 = 17'd0,
	output reg	[16:0]	RAMaddra_write_1 = 17'd0,
	output reg	[16:0]	RAMaddra_write_2 = 17'd0,
	output reg	[16:0]	RAMaddra_write_3 = 17'd0,
	output reg	[16:0]	RAMaddra_new_0 = 17'd0,
	output reg	[16:0]	RAMaddra_new_1 = 17'd0,
	output reg	[16:0]	RAMaddra_new_2 = 17'd0,
	output reg	[16:0]	RAMaddra_new_3 = 17'd0,
	output reg			flag_notbyte = 1'd0,
	output reg	[1:0]	state_ram = 2'd0,
	
	output reg 			flag_stop = 1'd0,    //给shx，拉高一个clk表示当前时帧有效数据接收完毕
	output reg [16:0]	addr_stop = 17'd0,   //给shx，拉高一个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐	
	
	//debug
	output	reg berstart_1d = 1'b0,
	output	reg bercompare = 1'b0,
	output	reg [16:0] bercount = 17'd0,
	output	reg [16:0] bercount_max = 17'd0,
	output	reg [16:0] ROMaddra_d2 = 17'd0,
	output	reg			RAMdout_d1 = 1'd0,
	
	// output	reg validnd_1_1d = 1'b0,
	// output	reg validnd_2_1d = 1'b0,
	output	reg validnd_new_new = 1'b0,
	// output	reg [63:0] stop_temp_1 = 64'd0,
	// output	reg [63:0] stop_temp_2 = 64'd0,
	output	reg [63:0] stop_temp_new = 64'd0,
	
	output				flag_stop_0,    //给shx，拉高1个clk表示当前时帧有效数据接收完毕
	output		[16:0]	addr_stop_0, 
	output	reg	[2:0]	cnt_8	= 3'b0,
	output	reg			state_8 = 1'd0,
	
	output rdy_scramble,
	output dout_scramble,
	
	output	reg [16:0]	RAMaddra   = 17'd0,   //比较误码率
	output  reg	[16:0]	ROMaddra   = 17'd0,   //比较误码率
	output	reg [0:0]	nd_ber   = 1'd0,   //比较误码率
    output  reg [63:0] recvNetData,
	output  reg recvNetDataNd
	// input [7:0] video_id01,
    // input [7:0] video_id02,
    // input [7:0] video_id03,
	// input	[7:0]	MAC_idNum
    );
	
	reg frameIDnd_d1 = 1'd0;
	reg frameIDnd_d2 = 1'd0;
	always @(posedge clk)begin
		frameIDnd_d1 <= frameIDnd;
		frameIDnd_d2 <= frameIDnd_d1;
	end
	
	// always @(posedge clk)begin
		// if(frameIDnd && !frameIDnd_d1)	flag_recvram <= ~flag_recvram;
		// else							flag_recvram <= flag_recvram;
	// end
	
	//-------------------------------------------------------------------------------------------------------------//
	
	// reg validnd_1 = 1'b0;
	// reg validnd_2 = 1'b0;
	reg validnd_new = 1'b0;
	reg [9:0] validlength = 10'd0;
    reg [6:0] cnt_net;
	reg [1:0] state_recv;
	reg nd_recvnet_dout;               
	always @(posedge clk)begin
		if(rst)begin
			// validnd_1 <= 1'b0;
			// validnd_2 <= 1'b0;
			state_recv <= 2'd0;
			validnd_new <= 1'b0;
			validlength <= 10'd0;
			cnt_net <= 6'd0;
			nd_recvnet_dout <= 1'd0;
		end
		else begin
			case(state_recv) 
				2'd0:begin				
					if(!validnd_new)begin				
						if(sync)begin	
							validnd_new <= 1'b1;
							nd_recvnet_dout <= 1'b1;
						end
						else begin		
							validnd_new <= 1'b0;
						end
					end
					else begin
						if(cnt_net == 6'd63) begin
							validlength <= validlength + 10'd1;
							if(validlength == 10'd1023)begin
								validnd_new <= 1'b0;
								state_recv <= 2'd1;
							end else begin
								validnd_new <= 1'b1;
								state_recv <= state_recv;
							end	
							nd_recvnet_dout <= 1'b0;
							cnt_net <= 6'd63;
						end
						else begin
							state_recv <= state_recv;
							nd_recvnet_dout <= 1'b1;
							cnt_net <= cnt_net +6'd1;
							validlength <= validlength + 10'd1;
							if(validlength == 10'd1023)begin
								validnd_new <= 1'b0;
							end else begin
								validnd_new <= 1'b1;
							end
						end
						
					end	
				end
				2'd1:begin
					if(!validnd_new)begin				
						if(sync)begin	
							validnd_new <= 1'b1;
						end
						else begin		
							validnd_new <= 1'b0;
						end
						state_recv <= state_recv;
					end
					else begin
						state_recv <= state_recv;
						nd_recvnet_dout <= 1'b0;
						cnt_net <= 6'd0;
						validlength <= validlength + 10'd1;
						if(validlength == 10'd1023)begin
							validnd_new <= 1'b0;
						end else begin
							validnd_new <= 1'b1;
						end
					end
				end
				default:begin
             
					if(!validnd_new)begin				
						if(sync)begin	
                                        
							validnd_new <= 1'b1;
                      
							nd_recvnet_dout <= 1'b1;
						end
						else begin		
							validnd_new <= 1'b0;
						end
					end
					else begin
						if(cnt_net == 6'd63) begin
							validlength <= validlength + 10'd1;
							if(validlength == 10'd1023)begin
								validnd_new <= 1'b0;
								state_recv <= 2'd1;
							end else begin
								validnd_new <= 1'b1;
								state_recv <= state_recv;
							end	
							nd_recvnet_dout <= 1'b0;
							cnt_net <= 6'd63;
						end
						else begin
							state_recv <= state_recv;
							nd_recvnet_dout <= 1'b1;
							cnt_net <= cnt_net +6'd1;
							validlength <= validlength + 10'd1;
							if(validlength == 10'd1023)begin
								validnd_new <= 1'b0;
							end else begin
								validnd_new <= 1'b1;
							end
						end
						
					end	
				end
			endcase
		end
	end
	
	// reg [15:0] RAMaddra_1 = 16'd0;
	// reg [15:0] RAMaddra_2 = 16'd0;
	// reg [16:0] RAMaddra_new = 17'd0;
	// reg [15:0] RAMaddra   = 16'd0;   //比较误码率
	reg [0:0] dout_scramble_d1   = 1'd0;   //比较误码率
	// reg [0:0] nd_ber   = 1'd0;   //比较误码率
	// reg validnd_1_1d = 1'b0;
	// reg validnd_2_1d = 1'b0;
	reg validnd_new_1d = 1'b0;
	always @(posedge clk)begin
		if(rst)begin
			// RAMaddra_1 <= 16'd0;
			// RAMaddra_2 <= 16'd0;
			// RAMaddra_new <= RAMaddra_new;
			RAMaddra     <= 17'd0;	//比较误码率
			ROMaddra     <= 17'd0;	//比较误码率
			dout_scramble_d1   <= 1'd0;	//比较误码率
			nd_ber	   <= 1'd0;	//比较误码率
			// validnd_1_1d <= 1'b0;
			// validnd_2_1d <= 1'b0;			
			validnd_new_1d <= 1'b0;			
		end else begin
			// validnd_1_1d <= validnd_1;
			// if(validnd_1_1d) begin
				// RAMaddra_1	<= RAMaddra_1 + 16'd1;					
			// end else begin
				// RAMaddra_1	<= RAMaddra_1;
			// end

			// validnd_2_1d <= validnd_2;			
			// if(validnd_2_1d) begin
				// RAMaddra_2	<= RAMaddra_2 + 16'd1;					
			// end else begin
				// RAMaddra_2	<= RAMaddra_2;
			// end
			
			validnd_new_1d <= validnd_new;			
			// if(validnd_new_1d) begin
				// RAMaddra_new	<= RAMaddra_new + 16'd1;					
			// end else begin
				// RAMaddra_new	<= RAMaddra_new;
			// end
			
			//比较误码率
			// if(validnd_1_1d||validnd_2_1d) begin	
			if(validnd_new_1d) begin	
				RAMaddra	<= RAMaddra + 17'd1;		
				ROMaddra	<= ROMaddra + 17'd1;
				dout_scramble_d1 <= dout_scramble;
				nd_ber		<= 1'd1;
			end
			else begin
				RAMaddra	<= RAMaddra;	
				ROMaddra	<= ROMaddra;
				dout_scramble_d1 <= dout_scramble_d1;
				nd_ber		<= 1'd0;
			end
			//比较误码率	
		end
	end
	
	reg nd_recvnet_dout_d1;
	reg nd_recvnet_dout_d2;
	reg nd_recvnet_dout_d3;
	reg nd_recvnet_dout_d4;
	
	reg wr_en_232;
	reg rs232_send;
	reg [4:0] cnt_422_wait;
	wire validnd_new_delay;
	reg validnd_new_delay_d1;
	wire framedata;
	reg framedata_d1;
    reg [7:0] data_net_byte  [87:0];
    reg [7:0] clk_net_byte;
    reg [9:0] clk_net_bit;
	//shiftram_scramble shiftram_scramble(.CLK(clk),.D({dout_scramble,validnd_new}),.Q({framedata,validnd_new_delay}));
	reg [7:0] cnt_422_net;
	always @(posedge clk)begin
		if(rst2)begin
			state_ram		<= 2'd0;
			RAMaddra_new_0	<= 17'd0;
			RAMaddra_new_1	<= 17'd0;
			RAMaddra_new_2	<= 17'd0;
			RAMaddra_new_3	<= 17'd0;
			flag_notbyte	<= 1'd0;
			nd_recvnet_dout_d1 <= 1'd0;
			nd_recvnet_dout_d2 <= 1'd0;
			nd_recvnet_dout_d3 <= 1'd0;
			nd_recvnet_dout_d4 <= 1'd0;
			recvNetDataNd <= 1'd0;
			recvNetData <= 64'd0;
			wr_en_232	<= 1'b0;
			rs232_send <= 1'b0;
			cnt_422_wait <= 5'd0;
			cnt_422_net <= 8'd0;
            clk_net_bit <= 10'd0;
            clk_net_byte <= 8'd0;
            validnd_new_delay_d1 <= 1'b0;
            framedata_d1 <= 1'b0;
		end
		else begin
            framedata_d1 <= framedata;
            validnd_new_delay_d1 <= validnd_new_delay;   
			nd_recvnet_dout_d1 <= nd_recvnet_dout;
			nd_recvnet_dout_d2 <= nd_recvnet_dout_d1;
			nd_recvnet_dout_d3 <= nd_recvnet_dout_d2;
			nd_recvnet_dout_d4 <= nd_recvnet_dout_d3;
			if(!nd_recvnet_dout_d1 && nd_recvnet_dout_d2) begin//检测到网络层数据传输完毕拉高2个clk recvNetDataNd
				recvNetDataNd <= 1'b1;
			end
			else begin
				if(!nd_recvnet_dout_d3 && nd_recvnet_dout_d4) begin//延迟2个clk确保50MHz采到recvNetDataNd再拉低
					recvNetDataNd <= 1'b0;
				end
				else begin
					recvNetDataNd <= recvNetDataNd;
				end
			end
			case(state_ram)
			//有了新的一帧，准备开始存储
			2'd0:begin
				if(frameIDnd_d2) begin
					state_ram	<= 2'd1;
					RAMaddra_new_0<= RAMaddra_new_0;
					RAMaddra_new_1<= RAMaddra_new_1;
                    RAMaddra_new_2 <= RAMaddra_new_2;
                    RAMaddra_new_3 <= RAMaddra_new_3;
				end
				else begin
					state_ram	<= state_ram;
					RAMaddra_new_0<= RAMaddra_new_0;
					RAMaddra_new_1<= RAMaddra_new_1;
                    RAMaddra_new_2 <= RAMaddra_new_2;
                    RAMaddra_new_3 <= RAMaddra_new_3;
				end
				validnd_new_new <= 1'd0;
				flag_notbyte	<= 1'd0;				
			end
			2'd1:begin
				if(flag_stop_0) begin
                    if(recvNetData[63:56] == 8'd2 && recvNetData[23:0]==24'h7E5A33) begin
                        RAMaddra_new_0	<= addr_stop_0 +17'd1;
                    end
                    else if(recvNetData[63:56] == 8'd3 && recvNetData[23:0]==24'h7E5A33) begin
                        RAMaddra_new_1	<= addr_stop_0 +17'd1;
                    end
                    else if(recvNetData[63:56] == 8'd4 && recvNetData[23:0]==24'h7E5A33) begin
                        RAMaddra_new_2	<= addr_stop_0 +17'd1;
                    end
                    else if(recvNetData[63:56] == 8'hff && recvNetData[23:0]==24'h7E5A33) begin
                        RAMaddra_new_3	<= addr_stop_0 +17'd1;
                    end
                    else begin
                        RAMaddra_new_0 <= RAMaddra_new_0;
                        RAMaddra_new_1 <= RAMaddra_new_1;
                        RAMaddra_new_2 <= RAMaddra_new_2;
                        RAMaddra_new_3 <= RAMaddra_new_3;
                    end
					validnd_new_new <= 1'd0;
					state_ram		<= 2'd2;					
				end
				else begin
					state_ram		<= state_ram;
					validnd_new_new <= validnd_new;	                 
					if(validnd_new_new) begin
						if(nd_recvnet_dout_d1) begin
							recvNetData[63:0] <= {dout_scramble,recvNetData[63:1]};
						end
						else begin
                            if(recvNetData[63:56] == 8'd2 && recvNetData[23:0]==24'h7E5A33) begin
                                RAMaddra_new_0 <= RAMaddra_new_0 + 17'd1;
                                RAMaddra_new_1 <= RAMaddra_new_1;
                                RAMaddra_new_2 <= RAMaddra_new_2;
                                RAMaddra_new_3 <= RAMaddra_new_3;
                            end
                            else if(recvNetData[63:56] == 8'd3 && recvNetData[23:0]==24'h7E5A33) begin
                                RAMaddra_new_0 <= RAMaddra_new_0;
                                RAMaddra_new_1 <= RAMaddra_new_1 + 17'd1;
                                RAMaddra_new_2 <= RAMaddra_new_2;
                                RAMaddra_new_3 <= RAMaddra_new_3;
                            end
                            else if(recvNetData[63:56] == 8'd4 && recvNetData[23:0]==24'h7E5A33) begin
                                RAMaddra_new_0 <= RAMaddra_new_0;
                                RAMaddra_new_1 <= RAMaddra_new_1;
                                RAMaddra_new_2 <= RAMaddra_new_2 + 17'd1;
                                RAMaddra_new_3 <= RAMaddra_new_3;
                            end
                            else if(recvNetData[63:56] == 8'hff && recvNetData[23:0]==24'h7E5A33) begin
                                RAMaddra_new_0 <= RAMaddra_new_0;
                                RAMaddra_new_1 <= RAMaddra_new_1;
                                RAMaddra_new_2 <= RAMaddra_new_2;
                                RAMaddra_new_3 <= RAMaddra_new_3 + 17'd1;
                            end
                            else begin
                                RAMaddra_new_0 <= RAMaddra_new_0;
                                RAMaddra_new_1 <= RAMaddra_new_1;
                                RAMaddra_new_2 <= RAMaddra_new_2;
                                RAMaddra_new_3 <= RAMaddra_new_3;
                            end
						end
					end 
                    else begin
                        RAMaddra_new_0 <= RAMaddra_new_0;
						RAMaddra_new_1 <= RAMaddra_new_1;
						RAMaddra_new_2 <= RAMaddra_new_2;
						RAMaddra_new_3 <= RAMaddra_new_3;
					end
				end
				flag_notbyte	<= 1'd0;
			end
			2'd2:begin
				//  rs232_send <= 1'b0;
				state_ram		<= 2'd0;
                if(recvNetData[63:56] == 8'd2 && recvNetData[23:0]==24'h7E5A33) begin
                    case(RAMaddra_new_0[2:0])
                    3'b000:begin
                        flag_notbyte <= 1'd0;
                        RAMaddra_new_0 <= RAMaddra_new_0;
                    end
                    3'b001:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_0 <= RAMaddra_new_0+17'd7;
                    end
                    3'b010:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_0 <= RAMaddra_new_0+17'd6;
                    end
                    3'b011:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_0 <= RAMaddra_new_0+17'd5;
                    end
                    3'b100:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_0 <= RAMaddra_new_0+17'd4;
                    end
                    3'b101:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_0 <= RAMaddra_new_0+17'd3;
                    end
                    3'b110:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_0 <= RAMaddra_new_0+17'd2;
                    end
                    3'b111:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_0 <= RAMaddra_new_0+17'd1;
                    end
                    endcase
                 end
                 else if(recvNetData[63:56] == 8'd3 && recvNetData[23:0]==24'h7E5A33) begin
                    case(RAMaddra_new_1[2:0])
                    3'b000:begin
                        flag_notbyte <= 1'd0;
                        RAMaddra_new_1 <= RAMaddra_new_1;
                    end
                    3'b001:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_1 <= RAMaddra_new_1+17'd7;
                    end
                    3'b010:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_1 <= RAMaddra_new_1+17'd6;
                    end
                    3'b011:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_1 <= RAMaddra_new_1+17'd5;
                    end
                    3'b100:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_1 <= RAMaddra_new_1+17'd4;
                    end
                    3'b101:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_1 <= RAMaddra_new_1+17'd3;
                    end
                    3'b110:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_1 <= RAMaddra_new_1+17'd2;
                    end
                    3'b111:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_1 <= RAMaddra_new_1+17'd1;
                    end
                    endcase
                 end
                 else if(recvNetData[63:56] == 8'd4 && recvNetData[23:0]==24'h7E5A33) begin
                    case(RAMaddra_new_2[2:0])
                    3'b000:begin
                        flag_notbyte <= 1'd0;
                        RAMaddra_new_2 <= RAMaddra_new_2;
                    end
                    3'b001:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_2 <= RAMaddra_new_2+17'd7;
                    end
                    3'b010:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_2 <= RAMaddra_new_2+17'd6;
                    end
                    3'b011:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_2 <= RAMaddra_new_2+17'd5;
                    end
                    3'b100:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_2 <= RAMaddra_new_2+17'd4;
                    end
                    3'b101:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_2 <= RAMaddra_new_2+17'd3;
                    end
                    3'b110:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_2 <= RAMaddra_new_2+17'd2;
                    end
                    3'b111:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_2 <= RAMaddra_new_2+17'd1;
                    end
                    endcase
                 end
                 else if(recvNetData[63:56] == 8'hff&& recvNetData[23:0]==24'h7E5A33) begin
                    case(RAMaddra_new_3[2:0])
                    3'b000:begin
                        flag_notbyte <= 1'd0;
                        RAMaddra_new_3 <= RAMaddra_new_3;
                    end
                    3'b001:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_3 <= RAMaddra_new_3+17'd7;
                    end
                    3'b010:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_3 <= RAMaddra_new_3+17'd6;
                    end
                    3'b011:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_3 <= RAMaddra_new_3+17'd5;
                    end
                    3'b100:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_3 <= RAMaddra_new_3+17'd4;
                    end
                    3'b101:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_3 <= RAMaddra_new_3+17'd3;
                    end
                    3'b110:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_3 <= RAMaddra_new_3+17'd2;
                    end
                    3'b111:begin
                        flag_notbyte <= 1'd1;
                        RAMaddra_new_3 <= RAMaddra_new_3+17'd1;
                    end
                    endcase
                 end
                 else begin
                    flag_notbyte <= 1'b0;
                    RAMaddra_new_0 <= RAMaddra_new_0;
                    RAMaddra_new_1 <= RAMaddra_new_1;
                    RAMaddra_new_2 <= RAMaddra_new_2;
                    RAMaddra_new_3 <= RAMaddra_new_3;
                 end
                 
			end
			default:begin
				if(frameIDnd_d2) begin
					state_ram	<= 2'd1;
					RAMaddra_new_0 <= RAMaddra_new_0;
                    RAMaddra_new_1 <= RAMaddra_new_1;
                    RAMaddra_new_2 <= RAMaddra_new_2;
                    RAMaddra_new_3 <= RAMaddra_new_3;
				end
				else begin
					state_ram	<= state_ram;
					RAMaddra_new_0 <= RAMaddra_new_0;
                    RAMaddra_new_1 <= RAMaddra_new_1;
                    RAMaddra_new_2 <= RAMaddra_new_2;
                    RAMaddra_new_3 <= RAMaddra_new_3;
				end
				validnd_new_new <= 1'd0;
				flag_notbyte	<= 1'd0;
			end
			endcase
		end
	end

	
	reg [8:0] bagcnt = 9'd0;
	always @(posedge clk)begin
		if(rst)begin
			bagcnt <= 9'd0;
		end else begin
			if(sync)begin
				bagcnt <= bagcnt + 9'd1;
			end else begin
				bagcnt <= bagcnt;
			end
		end
	end
	
	wire scramblestart;
	assign scramblestart = (bagcnt == 9'd0)? sync : 1'b0;

	// wire rdy_scramble;
	// wire dout_scramble;
	Scramble Scramble (
		.clk(clk), 
		.rst(rst2 || framerdy),
		.start(scramblestart), 
		// .nd(validnd_1||validnd_2), 
		.nd(validnd_new), 
		.din(din), 
		.rdy(rdy_scramble), 
		.dout(dout_scramble)
		);			
		
	

	//------------------------------------------比较误码率---------------------------//
	reg [16:0] RAMaddrb = 17'd0;
	wire  RAMdout;
	RAM_merge RAM_merge_0 (
	  .clka(clk), // input clka
	  // .wea(validnd_1_1d||validnd_2_1d), // input [0 : 0] wea
	  .wea(validnd_new_1d), // input [0 : 0] wea
	  .addra(RAMaddra), // input [16 : 0] addra
	  .dina(dout_scramble), // input [0 : 0] dina
	  .clkb(clk), // input clkb
	  .addrb(RAMaddrb), // input [16 : 0] addrb
	  .doutb(RAMdout) // output [0 : 0] doutb
	);
	
	// reg [15:0] ROMaddra = 16'd0;
	wire  ROMdout;
	ROM_ber ROM_ber (
	  .clka(clk), // input clka
	  .addra(ROMaddra), // input [16 : 0] addra
	  .douta(ROMdout) // output [0 : 0] douta
	);
	
	reg berstart = 1'b0;
	always @(posedge clk)begin
		if(rst2)begin
			RAMaddrb	<= 17'd0;
			berstart	<= 1'b0;
		end else begin
			if(!berstart)begin
				RAMaddrb	<= 17'd0;
				if(bagcnt == 9'd105 && validlength == 10'd1023)begin
					berstart <= 1'b1;
				end else begin
					berstart <= 1'b0;
				end
			end else begin				
				if(RAMaddrb == 17'd107519)begin
					berstart	<= 1'b0;
					RAMaddrb	<= 17'd0;
				end else begin
					berstart <= 1'b1;
					RAMaddrb <= RAMaddrb + 17'd1;
				end
			end
		end
	end
	

	
	
	reg [16:0] ROMaddra_d1 = 17'd0;
	always @(posedge clk)begin
		berstart_1d <= berstart;	
		if(rst)begin	
			bercompare <= 1'b0;
			bercount <= 17'd0;
			ROMaddra_d1 <= 17'd0;
			ROMaddra_d2 <= 17'd0;
			RAMdout_d1  <= 1'd0;
			bercount_max <= bercount;
		end else begin
			if(nd_ber) begin
				bercompare <= dout_scramble_d1^ROMdout;
				bercount <= bercount + bercompare;
				
				ROMaddra_d1 <= ROMaddra;
				ROMaddra_d2 <= ROMaddra_d1;
				RAMdout_d1  <= dout_scramble_d1;
				bercount_max <= bercount_max;
			end
			else begin
				bercompare <= 1'd0;
				bercount <= bercount;
				
				ROMaddra_d1 <= ROMaddra_d1;
				ROMaddra_d2 <= ROMaddra_d2;
				RAMdout_d1  <= RAMdout_d1;
				bercount_max <= bercount_max;
			end
		end
	end
	//------------------------------------------比较误码率---------------------------//
	
	
	
	// RAM_recv RAM_recv_1 (
	  // .clka(clk), // input clka
	  // .wea(validnd_1_1d), // input [0 : 0] wea
	  // .addra(RAMaddra_1), // input [15 : 0] addra
	  // .dina(dout_scramble), // input [0 : 0] dina
	  // .clkb(clk2), // input clkb
	  // .addrb(recv_addr1), // input [12 : 0] addrb
	  // .doutb(recv_data1) // output [7 : 0] doutb
	// );

	// RAM_recv RAM_recv_2 (
	  // .clka(clk), // input clka
	  // .wea(validnd_2_1d), // input [0 : 0] wea
	  // .addra(RAMaddra_2), // input [15 : 0] addra
	  // .dina(dout_scramble), // input [0 : 0] dina
	  // .clkb(clk2), // input clkb
	  // .addrb(recv_addr2), // input [12 : 0] addrb
	  // .doutb(recv_data2) // output [7 : 0] doutb
	// );
	
	RAM_recvnew RAM_recvnew_0 (
	  .clka(clk), // input clka
	  .wea(validnd_new_new), // input [0 : 0] wea
	  .addra(RAMaddra_new_0), // input [16 : 0] addra
	  .dina(dout_scramble), // input [0 : 0] dina
	  .clkb(clk2), // input clkb
	  .addrb(recv_addr_new_0), // input [13 : 0] addrb
	  .doutb(recv_data_new_0) // output [7 : 0] doutb
	);
    
    RAM_recvnew RAM_recvnew_1 (
	  .clka(clk), // input clka
	  .wea(validnd_new_new), // input [0 : 0] wea
	  .addra(RAMaddra_new_1), // input [16 : 0] addra
	  .dina(dout_scramble), // input [0 : 0] dina
	  .clkb(clk2), // input clkb
	  .addrb(recv_addr_new_1), // input [13 : 0] addrb
	  .doutb(recv_data_new_1) // output [7 : 0] doutb
	);
    RAM_recvnew RAM_recvnew_2 (
	  .clka(clk), // input clka
	  .wea(validnd_new_new), // input [0 : 0] wea
	  .addra(RAMaddra_new_2), // input [16 : 0] addra
	  .dina(dout_scramble), // input [0 : 0] dina
	  .clkb(clk2), // input clkb
	  .addrb(recv_addr_new_2), // input [13 : 0] addrb
	  .doutb(recv_data_new_2) // output [7 : 0] doutb
	);
    /*RAM_recvnew RAM_recvnew_3 (
	  .clka(clk), // input clka
	  .wea(validnd_new_new), // input [0 : 0] wea
	  .addra(RAMaddra_new_3), // input [16 : 0] addra
	  .dina(dout_scramble), // input [0 : 0] dina
	  .clkb(clk2), // input clkb
	  .addrb(recv_addr_new_3), // input [13 : 0] addrb
	  .doutb(recv_data_new_3) // output [7 : 0] doutb
	);*/
	
	//-------------------------------------------------------------------------------------------------------------//
	
	//-------------------------------------找停止位---------------------------//
	
	
	// reg nd_stop_1 = 1'd0;
	// reg nd_stop_2 = 1'd0;
	reg nd_stop_new = 1'd0;
	
	// reg [15:0] RAMaddra_1_temp = 16'd0;
	// reg [15:0] RAMaddra_2_temp = 16'd0;
	reg [16:0] RAMaddra_new_temp = 17'd0;
	find_stop find_stop (
		.clk(clk), 
		// .nd_stop_1(nd_stop_1), 
		// .nd_stop_2(nd_stop_2), 
		.nd_stop_new(nd_stop_new), 
		// .RAMaddra_1_temp(RAMaddra_1_temp), 
		// .RAMaddra_2_temp(RAMaddra_2_temp), 
		.RAMaddra_new_temp(RAMaddra_new_temp), 
		// .stop_temp_1(stop_temp_1), 
		// .stop_temp_2(stop_temp_2), 
		.stop_temp_new(stop_temp_new), 
		
		.vio_stopbit(vio_stopbit),
		
		.flag_stop_0(flag_stop_0), 
		.addr_stop_0(addr_stop_0)
		);
	
	// reg [63:0] stop_temp_1 = 64'd0;
	// reg [63:0] stop_temp_2 = 64'd0;
	// reg			flag_stop_0 = 1'd0;    //给shx，拉高1个clk表示当前时帧有效数据接收完毕
	// reg	[15:0]	addr_stop_0 = 16'd0;   //给shx，拉高1个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐	
	always @(posedge clk)begin
		// nd_stop_1 <= validnd_1_1d;
		// nd_stop_2 <= validnd_2_1d;
		nd_stop_new <= validnd_new_1d;
		// if(validnd_1_1d) begin
			// stop_temp_1[0] <= dout_scramble;
			// stop_temp_1[63:1] <= stop_temp_1[62:0];
			// RAMaddra_1_temp <= RAMaddra_1;
			// RAMaddra_2_temp <= 16'd0;
		// end
		// else begin
			// if(validnd_2_1d) begin
				// stop_temp_2[0] <= dout_scramble;
				// stop_temp_2[63:1] <= stop_temp_2[62:0];
				// RAMaddra_1_temp <= 16'd0;
				// RAMaddra_2_temp <= RAMaddra_2;
			// end
			// else begin
				// stop_temp_1 <= stop_temp_1;
				// stop_temp_2 <= stop_temp_2;
				
				// RAMaddra_1_temp <= RAMaddra_1_temp;
				// RAMaddra_2_temp <= RAMaddra_2_temp;
			// end
		// end
		if(validnd_new_1d) begin
			stop_temp_new[0] <= dout_scramble;
			stop_temp_new[63:1] <= stop_temp_new[62:0];
            if(recvNetData[63:56] == 8'd2 && recvNetData[23:0]==24'h7E5A33) begin
                RAMaddra_new_temp <= RAMaddra_new_0;
            end
            else if(recvNetData[63:56] == 8'd3 && recvNetData[23:0]==24'h7E5A33) begin
                RAMaddra_new_temp <= RAMaddra_new_1;
            end
            else if(recvNetData[63:56] == 8'd4 && recvNetData[23:0]==24'h7E5A33) begin
                RAMaddra_new_temp <= RAMaddra_new_2;
            end
            else if(recvNetData[63:56] == 8'hff && recvNetData[23:0]==24'h7E5A33) begin
                RAMaddra_new_temp <= RAMaddra_new_3;
            end
            else begin
                RAMaddra_new_temp <= RAMaddra_new_temp;
            end
		end
		else begin
			stop_temp_new <= stop_temp_new;
			
			RAMaddra_new_temp <= RAMaddra_new_temp;
		end
	end
	
	
	// reg	[2:0]	cnt_8	= 3'b0;
	// reg			state_8 = 1'd0;
	always @(posedge clk)begin
		case(state_8)
		1'd0:begin
			if(flag_stop_0)begin
				cnt_8		<= 3'b0;
				flag_stop	<= 1'b1;
				addr_stop	<= addr_stop_0;
				state_8		<= 1'd1;
			end
			else begin
				cnt_8		<= 3'b0;
				flag_stop	<= 1'b0;
				addr_stop	<= addr_stop;
				state_8		<= state_8;
			end
		end
		1'd1:begin
			if(cnt_8==3'd7) begin
				cnt_8		<= 3'b0;
				flag_stop	<= 1'b0;
				addr_stop	<= addr_stop;
				state_8		<= 1'd0;
			end
			else begin
				cnt_8		<= 3'b1+cnt_8;
				flag_stop	<= 1'b1;
				addr_stop	<= addr_stop;
				state_8		<= state_8;
			end
		end
		endcase
	end
	
	
	reg [16:0] RAMaddra_new_0_d1 = 17'd0;
	reg [16:0] RAMaddra_new_1_d1 = 17'd0;
	reg [16:0] RAMaddra_new_2_d1 = 17'd0;
	reg [16:0] RAMaddra_new_3_d1 = 17'd0;
	always@(posedge clk2)begin
		RAMaddra_new_0_d1 <= RAMaddra_new_0;
		RAMaddra_new_1_d1 <= RAMaddra_new_1;
		RAMaddra_new_2_d1 <= RAMaddra_new_2;
		RAMaddra_new_3_d1 <= RAMaddra_new_3;
		RAMaddra_write_0  <= RAMaddra_new_0_d1;
		RAMaddra_write_1  <= RAMaddra_new_1_d1;
		RAMaddra_write_2  <= RAMaddra_new_2_d1;
		RAMaddra_write_3  <= RAMaddra_new_3_d1;
	end
	
	//-------------------------------------找停止位---------------------------//

	

	always @(posedge clk)begin
		if(rst2)begin
			framerdy	<= 1'b0;
		end else begin	
			if(bagcnt == 9'd105 && validlength == 10'd1023)begin
				framerdy <= 1'b1;
			end else begin
				framerdy <= 1'b0;
			end				
		end
	end
	
	ila_ber ila_ber(
		.clk(clk),
		.probe0(rst),
		.probe1(ROMdout),
		.probe2(validnd_new_delay),
		.probe3(bercount),
		.probe4(flag_stop_0),
		.probe5(framedata_d1),
		.probe6(recvNetDataNd),
		.probe7(addr_stop_0),
		.probe8(nd_recvnet_dout_d1),
		.probe9(recvNetData),
		.probe10(dout_scramble),
		.probe11(wr_en_232),
		.probe12(framedata),
		.probe13(data_net_byte[87]),
		.probe14(RAMaddra_new_0),
		.probe15(RAMaddra_new_1)
		
	);


endmodule