`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/11/18 23:18:07
// Design Name: 
// Module Name: CCSDS_LDPC_DEC_K1024_R12
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module CCSDS_LDPC_DEC_K1024_R12 #(
    parameter WIDTH = 4'd8,
    parameter MAX_ITER_NUM = 6'd14,
    parameter OUT_ONLY_INFORMATION = 1'b0  //译码输出格式选择标志，1:只输出信息位；0：输出整个码字
) (
    input             clk,        //工作时钟,100MHz
    input             Rst,        //同步复位信号,高有效
    input             FrameSync,  //帧同步标志,高脉冲
    input             Nd,         //译码输入数据有效标志,高有效
    input [WIDTH-1:0] Din,        //译码输入数据,软信息,数据速率约为12.5Mbps

    output reg       LDPC_SyncOut = 1'b0,  //LDPC模块帧同步输出信号,高脉冲,指示帧起点
    output reg       Rdy = 1'b0,           //译码输出信号有效标志,高有效
    output reg [0:0] LDPC_Dout = 1'b0,     //译码输出信号
    output reg [8:0] good_frames = 9'd0,   //译码好帧计数
    output reg [8:0] bad_frames = 9'd0,    //译码坏帧计数
    output reg [8:0] total_frames = 9'd0   //译码总帧计数
);

    reg              rst_MS = 1'd0;
    reg              framesync_MS = 1'd0;
    reg              nd_MS = 1'd0;
    reg  [WIDTH-1:0] din_MS = 8'd0;
    reg              oe_MS = 1'd0;
    wire             deal_end_MS;
    wire [WIDTH-1:0] dout01_MS;
    wire [WIDTH-1:0] dout02_MS;
    wire [WIDTH-1:0] dout03_MS;
    wire [WIDTH-1:0] dout04_MS;

    always @(posedge clk) begin
        rst_MS       <= Rst;
        framesync_MS <= FrameSync;
        nd_MS        <= Nd;
        din_MS       <= Din;
    end
    //******输入数据的缓存模块
    Message_Store #(
        .WIDTH(WIDTH)
    ) MS (
        .clk         (clk),
        .rst_MS      (rst_MS),
        .framesync_MS(framesync_MS),
        .nd_MS       (nd_MS),
        .din_MS      (din_MS),
        .oe_MS       (oe_MS),
        .deal_end_MS (deal_end_MS),
        .syncout_MS  (syncout_MS),
        .rdy_MS      (rdy_MS),
        .dout01_MS   (dout01_MS),
        .dout02_MS   (dout02_MS),
        .dout03_MS   (dout03_MS),
        .dout04_MS   (dout04_MS)
    );

    reg              rst = 1'd0;
    reg              start = 1'd0;
    reg              framesync = 1'd0;
    reg              nd = 1'd0;

    reg  [WIDTH-1:0] din01 = 8'd0;
    reg  [WIDTH-1:0] din02 = 8'd0;
    reg  [WIDTH-1:0] din03 = 8'd0;
    reg  [WIDTH-1:0] din04 = 8'd0;

    wire             ask_din;
    wire [      8:0] gd_frames;
    wire [      8:0] bd_frames;
    wire [      8:0] tl_frames;

    wire             ldpc_syncout;
    wire             rdy;
    wire [      0:0] ldpc_dout;

    always @(posedge clk) begin
        rst       <= Rst;
        start     <= deal_end_MS;
        framesync <= syncout_MS;
        nd        <= rdy_MS;

        din01     <= dout01_MS;
        din02     <= dout02_MS;
        din03     <= dout03_MS;
        din04     <= dout04_MS;

        oe_MS     <= ask_din;
    end
    // TOP层译码器输出
    always @(posedge clk) begin
        LDPC_SyncOut <= ldpc_syncout;
        Rdy          <= rdy;
        LDPC_Dout    <= ldpc_dout;
        good_frames  <= gd_frames;
        bad_frames   <= bd_frames;
        total_frames <= tl_frames;
    end
    LDPC_DEC_PRO  //译码器的吞吐量=(信息比特数/(一次迭代所需的时钟数*迭代次数))*FPGA工作主频
    #(
        .MAX_ITER_NUM(MAX_ITER_NUM),
        .WIDTH(WIDTH),
        .OUT_ONLY_INFORMATION(OUT_ONLY_INFORMATION)
    ) LDPC_DEC (
        .clk         (clk),
        .rst         (rst),
        .start       (start),
        .framesync   (framesync),
        .nd          (nd),
        .din01       (din01),
        .din02       (din02),
        .din03       (din03),
        .din04       (din04),
        .ask_din     (ask_din),
        .gd_frames   (gd_frames),
        .bd_frames   (bd_frames),
        .tl_frames   (tl_frames),
        .ldpc_syncout(ldpc_syncout),
        .rdy         (rdy),
        .ldpc_dout   (ldpc_dout)
    );


endmodule