`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 2019/11/18 23:18:07 // Design Name: // Module Name: LDPC_DEC_PRO // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module LDPC_DEC_PRO #( parameter MAX_ITER_NUM = 6'd14, parameter WIDTH = 4'd8, parameter OUT_ONLY_INFORMATION = 1'd0 ) ( input clk, //工作时钟 input rst, //同步复位信号， 高有效 input start, //开始译码标志， 高脉冲 input framesync, //帧同步标志，高脉冲 input nd, //译码输入数据有效标志，高有效 input [WIDTH-1:0] din01, //译码输入数据， 软信息， 对应时刻 N input [WIDTH-1:0] din02, //译码输入数据， 软信息， 对应时刻 N+1*512 input [WIDTH-1:0] din03, //译码输入数据， 软信息， 对应时刻 N+2*512 input [WIDTH-1:0] din04, //译码输入数据， 软信息， 对应时刻 N+3*512 output reg ask_din = 1'd0, //向上层索要译码数据标志，高脉冲 output reg [8:0] gd_frames = 9'd0, //译码好帧计数 output reg [8:0] bd_frames = 9'd0, //译码坏帧计数 output reg [8:0] tl_frames = 9'd0, //译码总帧数计数 output reg ldpc_syncout = 1'd0, //LDPC 模块帧同步输出信号，高脉冲，指示帧起点 output reg rdy = 1'd0, //译码输出信号有效标志，高有效 output reg ldpc_dout = 1'd0 //译码输出信号 ); //*****列更新模块信号定义 reg rst_VN = 1'd0; reg start_VN = 1'd0; reg start_frame_VN = 1'd0; //7.23 xhx 在新的一帧数据来临前清零迭代次数的计数 reg [WIDTH-1:0] CHNL_dout_01_VN = 8'd0; //信道信息输入 reg [WIDTH-1:0] CHNL_dout_02_VN = 8'd0; reg [WIDTH-1:0] CHNL_dout_03_VN = 8'd0; reg [WIDTH-1:0] CHNL_dout_04_VN = 8'd0; reg [WIDTH-1:0] CN1_dout_01_00_VN = 8'd0; reg [WIDTH-1:0] CN1_dout_02_00_VN = 8'd0; //后面的00代表H阵原模图的IM reg [WIDTH-1:0] CN1_dout_02_01_VN = 8'd0; //后面的01代表H阵原模图的II1 reg [WIDTH-1:0] CN2_dout_01_00_VN = 8'd0; reg [WIDTH-1:0] CN2_dout_02_00_VN = 8'd0; reg [WIDTH-1:0] CN2_dout_03_00_VN = 8'd0; reg [WIDTH-1:0] CN2_dout_04_02_VN = 8'd0; //后面的02代表H阵原模图的II2 reg [WIDTH-1:0] CN2_dout_04_03_VN = 8'd0; //后面的03代表H阵原模图的II3 reg [WIDTH-1:0] CN2_dout_04_04_VN = 8'd0; //后面的04代表H阵原模图的II4 reg [WIDTH-1:0] CN3_dout_01_00_VN = 8'd0; reg [WIDTH-1:0] CN3_dout_02_05_VN = 8'd0; //后面的05代表H阵原模图的II5 reg [WIDTH-1:0] CN3_dout_02_06_VN = 8'd0; //后面的06代表H阵原模图的II6 reg [WIDTH-1:0] CN3_dout_03_07_VN = 8'd0; //后面的07代表H阵原模图的II7 reg [WIDTH-1:0] CN3_dout_03_08_VN = 8'd0; //后面的08代表H阵原模图的II8 reg [WIDTH-1:0] CN3_dout_04_00_VN = 8'd0; wire data_start_VN; wire data_start_ck_VN; wire end_VN; wire ask_din_VN; wire VN_wea_VN; wire [ 9:0] CN1_addr_rd_02_00_VN; wire [ 9:0] CN1_addr_rd_02_01_VN; wire [ 9:0] CN2_addr_rd_04_02_VN; wire [ 9:0] CN2_addr_rd_04_03_VN; wire [ 9:0] CN3_addr_rd_02_05_VN; wire [ 9:0] CN3_addr_rd_02_06_VN; wire [ 9:0] CN3_addr_rd_03_07_VN; wire [ 9:0] CN3_addr_rd_03_08_VN; wire [ 8:0] CN1_addr_rd_01_00_VN; wire [ 8:0] CN2_addr_rd_01_00_VN; wire [ 8:0] CN2_addr_rd_02_00_VN; wire [ 8:0] CN2_addr_rd_03_00_VN; wire [ 8:0] CN2_addr_rd_04_04_VN; wire [ 8:0] CN3_addr_rd_01_00_VN; wire [ 8:0] CN3_addr_rd_04_00_VN; wire [ 8:0] VN1_addr_wr_01_00_VN; wire [ 9:0] VN1_addr_wr_02_00_VN; wire [ 9:0] VN1_addr_wr_02_01_VN; wire [ 8:0] VN2_addr_wr_01_00_VN; wire [ 8:0] VN2_addr_wr_02_00_VN; wire [ 8:0] VN2_addr_wr_03_00_VN; wire [ 9:0] VN2_addr_wr_04_02_VN; wire [ 9:0] VN2_addr_wr_04_03_VN; wire [ 8:0] VN2_addr_wr_04_04_VN; wire [ 8:0] VN3_addr_wr_01_00_VN; wire [ 9:0] VN3_addr_wr_02_05_VN; wire [ 9:0] VN3_addr_wr_02_06_VN; wire [ 9:0] VN3_addr_wr_03_07_VN; wire [ 9:0] VN3_addr_wr_03_08_VN; wire [ 8:0] VN3_addr_wr_04_00_VN; wire [WIDTH-1:0] VN1_din_01_00_VN; wire [WIDTH-1:0] VN1_din_02_00_VN; wire [WIDTH-1:0] VN1_din_02_01_VN; wire [WIDTH-1:0] VN2_din_01_00_VN; wire [WIDTH-1:0] VN2_din_02_00_VN; wire [WIDTH-1:0] VN2_din_03_00_VN; wire [WIDTH-1:0] VN2_din_04_02_VN; wire [WIDTH-1:0] VN2_din_04_03_VN; wire [WIDTH-1:0] VN2_din_04_04_VN; wire [WIDTH-1:0] VN3_din_01_00_VN; wire [WIDTH-1:0] VN3_din_02_05_VN; wire [WIDTH-1:0] VN3_din_02_06_VN; wire [WIDTH-1:0] VN3_din_03_07_VN; wire [WIDTH-1:0] VN3_din_03_08_VN; wire [WIDTH-1:0] VN3_din_04_00_VN; wire DR_wea_VN; wire [ 8:0] DR_addr_wr_VN; wire DR_din_01_VN; wire DR_din_02_VN; wire DR_din_03_VN; wire DR_din_04_VN; wire DR_din_05_VN; //*****行更新模块信号定义 reg start_CN = 1'd0; //模块启动信号，高脉冲 reg rst_CN = 1'd0; reg [WIDTH-1:0] VN1_dout_01_00_CN = 8'd0; reg [WIDTH-1:0] VN1_dout_02_00_CN = 8'd0; //后面的00代表H阵原模图的IM reg [WIDTH-1:0] VN1_dout_02_01_CN = 8'd0; //后面的01代表H阵原模图的II1 reg [WIDTH-1:0] VN2_dout_01_00_CN = 8'd0; reg [WIDTH-1:0] VN2_dout_02_00_CN = 8'd0; reg [WIDTH-1:0] VN2_dout_03_00_CN = 8'd0; reg [WIDTH-1:0] VN2_dout_04_02_CN = 8'd0; //后面的02代表H阵原模图的II2 reg [WIDTH-1:0] VN2_dout_04_03_CN = 8'd0; //后面的03代表H阵原模图的II3 reg [WIDTH-1:0] VN2_dout_04_04_CN = 8'd0; //后面的04代表H阵原模图的II4 reg [WIDTH-1:0] VN3_dout_01_00_CN = 8'd0; reg [WIDTH-1:0] VN3_dout_02_05_CN = 8'd0; //后面的05代表H阵原模图的II5 reg [WIDTH-1:0] VN3_dout_02_06_CN = 8'd0; //后面的06代表H阵原模图的II6 reg [WIDTH-1:0] VN3_dout_03_07_CN = 8'd0; //后面的07代表H阵原模图的II7 reg [WIDTH-1:0] VN3_dout_03_08_CN = 8'd0; //后面的08代表H阵原模图的II8 reg [WIDTH-1:0] VN3_dout_04_00_CN = 8'd0; wire [ 9:0] VN1_addr_rd_02_00_CN; wire [ 9:0] VN1_addr_rd_02_01_CN; wire [ 9:0] VN2_addr_rd_04_02_CN; wire [ 9:0] VN2_addr_rd_04_03_CN; wire [ 9:0] VN3_addr_rd_02_05_CN; wire [ 9:0] VN3_addr_rd_02_06_CN; wire [ 9:0] VN3_addr_rd_03_07_CN; wire [ 9:0] VN3_addr_rd_03_08_CN; wire [ 8:0] VN1_addr_rd_01_00_CN; wire [ 8:0] VN2_addr_rd_01_00_CN; wire [ 8:0] VN2_addr_rd_02_00_CN; wire [ 8:0] VN2_addr_rd_03_00_CN; wire [ 8:0] VN2_addr_rd_04_04_CN; wire [ 8:0] VN3_addr_rd_01_00_CN; wire [ 8:0] VN3_addr_rd_04_00_CN; wire CN_wea_CN; wire [ 8:0] CN1_addr_wr_01_00_CN; wire [ 9:0] CN1_addr_wr_02_00_CN; wire [ 9:0] CN1_addr_wr_02_01_CN; wire [ 8:0] CN2_addr_wr_01_00_CN; wire [ 8:0] CN2_addr_wr_02_00_CN; wire [ 8:0] CN2_addr_wr_03_00_CN; wire [ 9:0] CN2_addr_wr_04_02_CN; wire [ 9:0] CN2_addr_wr_04_03_CN; wire [ 8:0] CN2_addr_wr_04_04_CN; wire [ 8:0] CN3_addr_wr_01_00_CN; wire [ 9:0] CN3_addr_wr_02_05_CN; wire [ 9:0] CN3_addr_wr_02_06_CN; wire [ 9:0] CN3_addr_wr_03_07_CN; wire [ 9:0] CN3_addr_wr_03_08_CN; wire [ 8:0] CN3_addr_wr_04_00_CN; wire [WIDTH-1:0] CN1_din_01_00_CN; wire [WIDTH-1:0] CN1_din_02_00_CN; wire [WIDTH-1:0] CN1_din_02_01_CN; wire [WIDTH-1:0] CN2_din_01_00_CN; wire [WIDTH-1:0] CN2_din_02_00_CN; wire [WIDTH-1:0] CN2_din_03_00_CN; wire [WIDTH-1:0] CN2_din_04_02_CN; wire [WIDTH-1:0] CN2_din_04_03_CN; wire [WIDTH-1:0] CN2_din_04_04_CN; wire [WIDTH-1:0] CN3_din_01_00_CN; wire [WIDTH-1:0] CN3_din_02_05_CN; wire [WIDTH-1:0] CN3_din_02_06_CN; wire [WIDTH-1:0] CN3_din_03_07_CN; wire [WIDTH-1:0] CN3_din_03_08_CN; wire [WIDTH-1:0] CN3_din_04_00_CN; wire end_CN; //模块结束标志，高脉冲 //*****校验节点信息存储RAM信号定义 reg CN_wea = 1'd0; //RAM写地址，H阵第１行 reg [ 8:0] CN1_addr_wr_01_00 = 9'd511; reg [ 9:0] CN1_addr_wr_02_00 = 10'd1023; reg [ 9:0] CN1_addr_wr_02_01 = 10'd511; //RAM写地址，H阵第２行 reg [ 8:0] CN2_addr_wr_01_00 = 9'd511; reg [ 8:0] CN2_addr_wr_02_00 = 9'd511; reg [ 8:0] CN2_addr_wr_03_00 = 9'd511; reg [ 9:0] CN2_addr_wr_04_02 = 10'd1023; reg [ 9:0] CN2_addr_wr_04_03 = 10'd511; reg [ 8:0] CN2_addr_wr_04_04 = 9'd511; //RAM写地址，H阵第３行 reg [ 8:0] CN3_addr_wr_01_00 = 9'd511; reg [ 9:0] CN3_addr_wr_02_05 = 10'd1023; reg [ 9:0] CN3_addr_wr_02_06 = 10'd511; reg [ 9:0] CN3_addr_wr_03_07 = 10'd1023; reg [ 9:0] CN3_addr_wr_03_08 = 10'd511; reg [ 8:0] CN3_addr_wr_04_00 = 9'd511; //RAM写数据，H阵第１行 reg [WIDTH-1:0] CN1_din_01_00 = 8'd0; reg [WIDTH-1:0] CN1_din_02_00 = 8'd0; reg [WIDTH-1:0] CN1_din_02_01 = 8'd0; //RAM写数据，H阵第２行 reg [WIDTH-1:0] CN2_din_01_00 = 8'd0; reg [WIDTH-1:0] CN2_din_02_00 = 8'd0; reg [WIDTH-1:0] CN2_din_03_00 = 8'd0; reg [WIDTH-1:0] CN2_din_04_02 = 8'd0; reg [WIDTH-1:0] CN2_din_04_03 = 8'd0; reg [WIDTH-1:0] CN2_din_04_04 = 8'd0; //RAM写数据，H阵第３行 reg [WIDTH-1:0] CN3_din_01_00 = 8'd0; reg [WIDTH-1:0] CN3_din_02_05 = 8'd0; reg [WIDTH-1:0] CN3_din_02_06 = 8'd0; reg [WIDTH-1:0] CN3_din_03_07 = 8'd0; reg [WIDTH-1:0] CN3_din_03_08 = 8'd0; reg [WIDTH-1:0] CN3_din_04_00 = 8'd0; //RAM读地址，H阵第１行 reg [ 8:0] CN1_addr_rd_01_00 = 9'd511; //RAM读地址，H阵第２行 reg [ 8:0] CN2_addr_rd_01_00 = 9'd511; reg [ 8:0] CN2_addr_rd_02_00 = 9'd511; //7.23 xhx 因为IM&II1，II2&II3,II5&II6,II7&II8是两两写在真双口RAM中，读写地址是同一个，需要分情况考虑 reg [ 8:0] CN2_addr_rd_03_00 = 9'd511; reg [ 8:0] CN2_addr_rd_04_04 = 9'd511; //RAM读地址，H阵第３行 reg [ 8:0] CN3_addr_rd_01_00 = 9'd511; reg [ 8:0] CN3_addr_rd_04_00 = 9'd511; //RAM数据输出，H阵第１行 wire [WIDTH-1:0] CN1_dout_01_00; wire [WIDTH-1:0] CN1_dout_02_00; //后面的00代表H阵原模图的IM wire [WIDTH-1:0] CN1_dout_02_01; //后面的01代表H阵原模图的II1 //RAM数据输出，H阵第２行 wire [WIDTH-1:0] CN2_dout_01_00; wire [WIDTH-1:0] CN2_dout_02_00; wire [WIDTH-1:0] CN2_dout_03_00; wire [WIDTH-1:0] CN2_dout_04_02; //后面的02代表H阵原模图的II2 wire [WIDTH-1:0] CN2_dout_04_03; //后面的03代表H阵原模图的II3 wire [WIDTH-1:0] CN2_dout_04_04; //后面的04代表H阵原模图的II4 //RAM数据输出，H阵第３行 wire [WIDTH-1:0] CN3_dout_01_00; wire [WIDTH-1:0] CN3_dout_02_05; //后面的05代表H阵原模图的II5 wire [WIDTH-1:0] CN3_dout_02_06; //后面的06代表H阵原模图的II6 wire [WIDTH-1:0] CN3_dout_03_07; //后面的07代表H阵原模图的II7 wire [WIDTH-1:0] CN3_dout_03_08; //后面的08代表H阵原模图的II8 wire [WIDTH-1:0] CN3_dout_04_00; //*****变量节点信息存储RAM信号定义 reg VN_wea = 1'd0; //RAM写地址，H阵第１行 reg [ 8:0] VN1_addr_wr_01_00 = 9'd511; reg [ 9:0] VN1_addr_wr_02_00 = 10'd1023; reg [ 9:0] VN1_addr_wr_02_01 = 10'd511; //RAM写地址，H阵第２行 reg [ 8:0] VN2_addr_wr_01_00 = 9'd511; reg [ 8:0] VN2_addr_wr_02_00 = 9'd511; reg [ 8:0] VN2_addr_wr_03_00 = 9'd511; reg [ 9:0] VN2_addr_wr_04_02 = 10'd1023; reg [ 9:0] VN2_addr_wr_04_03 = 10'd511; reg [ 8:0] VN2_addr_wr_04_04 = 9'd511; //RAM写地址，H阵第３行 reg [ 8:0] VN3_addr_wr_01_00 = 9'd511; reg [ 9:0] VN3_addr_wr_02_05 = 10'd1023; reg [ 9:0] VN3_addr_wr_02_06 = 10'd511; reg [ 9:0] VN3_addr_wr_03_07 = 10'd1023; reg [ 9:0] VN3_addr_wr_03_08 = 10'd511; reg [ 8:0] VN3_addr_wr_04_00 = 9'd511; //RAM写数据，H阵第１行 reg [WIDTH-1:0] VN1_din_01_00 = 8'd0; reg [WIDTH-1:0] VN1_din_02_00 = 8'd0; reg [WIDTH-1:0] VN1_din_02_01 = 8'd0; //RAM写数据，H阵第２行 reg [WIDTH-1:0] VN2_din_01_00 = 8'd0; reg [WIDTH-1:0] VN2_din_02_00 = 8'd0; reg [WIDTH-1:0] VN2_din_03_00 = 8'd0; reg [WIDTH-1:0] VN2_din_04_02 = 8'd0; reg [WIDTH-1:0] VN2_din_04_03 = 8'd0; reg [WIDTH-1:0] VN2_din_04_04 = 8'd0; //RAM写数据，H阵第３行 reg [WIDTH-1:0] VN3_din_01_00 = 8'd0; reg [WIDTH-1:0] VN3_din_02_05 = 8'd0; reg [WIDTH-1:0] VN3_din_02_06 = 8'd0; reg [WIDTH-1:0] VN3_din_03_07 = 8'd0; reg [WIDTH-1:0] VN3_din_03_08 = 8'd0; reg [WIDTH-1:0] VN3_din_04_00 = 8'd0; //RAM读地址，H阵第１行 reg [ 8:0] VN1_addr_rd_01_00 = 9'd511; //RAM读地址，H阵第２行 reg [ 8:0] VN2_addr_rd_01_00 = 9'd511; reg [ 8:0] VN2_addr_rd_02_00 = 9'd511; reg [ 8:0] VN2_addr_rd_03_00 = 9'd511; //7.23 xhx 同CN_RAM读地址 reg [ 8:0] VN2_addr_rd_04_04 = 9'd511; //RAM读地址，H阵第３行 reg [ 8:0] VN3_addr_rd_01_00 = 9'd511; reg [ 8:0] VN3_addr_rd_04_00 = 9'd511; //RAM数据输出，H阵第１行 wire [WIDTH-1:0] VN1_dout_01_00; wire [WIDTH-1:0] VN1_dout_02_00; //后面的00代表H阵原模图的IM wire [WIDTH-1:0] VN1_dout_02_01; //后面的01代表H阵原模图的II1 //RAM数据输出，H阵第２行 wire [WIDTH-1:0] VN2_dout_01_00; wire [WIDTH-1:0] VN2_dout_02_00; wire [WIDTH-1:0] VN2_dout_03_00; wire [WIDTH-1:0] VN2_dout_04_02; //后面的02代表H阵原模图的II2 wire [WIDTH-1:0] VN2_dout_04_03; //后面的03代表H阵原模图的II3 wire [WIDTH-1:0] VN2_dout_04_04; //后面的04代表H阵原模图的II4 //RAM数据输出，H阵第３行 wire [WIDTH-1:0] VN3_dout_01_00; wire [WIDTH-1:0] VN3_dout_02_05; //后面的05代表H阵原模图的II5 wire [WIDTH-1:0] VN3_dout_02_06; //后面的06代表H阵原模图的II6 wire [WIDTH-1:0] VN3_dout_03_07; //后面的07代表H阵原模图的II7 wire [WIDTH-1:0] VN3_dout_03_08; //后面的08代表H阵原模图的II8 wire [WIDTH-1:0] VN3_dout_04_00; //*****判决结果存储RAM信号定义 reg [ 0:0] DR_wea = 1'd0; reg [ 8:0] DR_addr_wr = 9'd511; reg [ 0:0] DR_din_01 = 1'd0; reg [ 0:0] DR_din_02 = 1'd0; reg [ 0:0] DR_din_03 = 1'd0; reg [ 0:0] DR_din_04 = 1'd0; // reg [0:0] DR_din_05=1'd0; reg [ 8:0] DR_addr_rd_01 = 9'd511; reg [ 8:0] DR_addr_rd_02 = 9'd511; reg [ 8:0] DR_addr_rd_03 = 9'd511; reg [ 8:0] DR_addr_rd_04 = 9'd511; // reg [8:0] DR_addr_rd_05=9'd511; wire DR_dout_01; wire DR_dout_02; wire DR_dout_03; wire DR_dout_04; // wire DR_dout_05; reg Switch_VN_CN = 1'd0; // Switch_VN_CN用于指示当前处于VN更新状态（值为0）还是CN更新状态（值为1） // 由于存储器用的是True dual RAM，因此要考虑读写地址线相同的RAM在VN及CN // 状态对应不同的地址，因此不能在上述两种状态下对其赋不同的值，故需要该 // 该变量指示当前状态。 always @(posedge clk) begin if (rst) Switch_VN_CN <= 1'd0; else begin if (start_VN) Switch_VN_CN <= 1'd0; else if (start_CN) Switch_VN_CN <= 1'd1; else Switch_VN_CN <= Switch_VN_CN; end end //******列更新模块 //输入信号 always @(posedge clk) begin rst_VN <= rst; start_VN <= (rst) ? 1'd0 : ((start || end_CN) ? 1'd1 : 1'd0); start_frame_VN <= start; CHNL_dout_01_VN <= din01; CHNL_dout_02_VN <= din02; CHNL_dout_03_VN <= din03; CHNL_dout_04_VN <= din04; CN1_dout_01_00_VN <= CN1_dout_01_00; CN1_dout_02_00_VN <= CN1_dout_02_00; CN1_dout_02_01_VN <= CN1_dout_02_01; CN2_dout_01_00_VN <= CN2_dout_01_00; CN2_dout_02_00_VN <= CN2_dout_02_00; CN2_dout_03_00_VN <= CN2_dout_03_00; CN2_dout_04_02_VN <= CN2_dout_04_02; CN2_dout_04_03_VN <= CN2_dout_04_03; CN2_dout_04_04_VN <= CN2_dout_04_04; CN3_dout_01_00_VN <= CN3_dout_01_00; CN3_dout_02_05_VN <= CN3_dout_02_05; CN3_dout_02_06_VN <= CN3_dout_02_06; CN3_dout_03_07_VN <= CN3_dout_03_07; CN3_dout_03_08_VN <= CN3_dout_03_08; CN3_dout_04_00_VN <= CN3_dout_04_00; end // 输出信号 // Switch_VN_CN用于指示当前处于VN更新状态（值为0）还是CN更新状态（值为1） always @(posedge clk) begin CN1_addr_wr_02_00 <= (Switch_VN_CN == 1'd0) ? CN1_addr_rd_02_00_VN : CN1_addr_wr_02_00_CN; CN1_addr_wr_02_01 <= (Switch_VN_CN == 1'd0) ? CN1_addr_rd_02_01_VN : CN1_addr_wr_02_01_CN; CN2_addr_wr_04_02 <= (Switch_VN_CN == 1'd0) ? CN2_addr_rd_04_02_VN : CN2_addr_wr_04_02_CN; CN2_addr_wr_04_03 <= (Switch_VN_CN == 1'd0) ? CN2_addr_rd_04_03_VN : CN2_addr_wr_04_03_CN; CN3_addr_wr_02_05 <= (Switch_VN_CN == 1'd0) ? CN3_addr_rd_02_05_VN : CN3_addr_wr_02_05_CN; CN3_addr_wr_02_06 <= (Switch_VN_CN == 1'd0) ? CN3_addr_rd_02_06_VN : CN3_addr_wr_02_06_CN; CN3_addr_wr_03_07 <= (Switch_VN_CN == 1'd0) ? CN3_addr_rd_03_07_VN : CN3_addr_wr_03_07_CN; CN3_addr_wr_03_08 <= (Switch_VN_CN == 1'd0) ? CN3_addr_rd_03_08_VN : CN3_addr_wr_03_08_CN; CN1_addr_rd_01_00 <= CN1_addr_rd_01_00_VN; CN2_addr_rd_01_00 <= CN2_addr_rd_01_00_VN; CN2_addr_rd_02_00 <= CN2_addr_rd_02_00_VN; CN2_addr_rd_03_00 <= CN2_addr_rd_03_00_VN; CN2_addr_rd_04_04 <= CN2_addr_rd_04_04_VN; CN3_addr_rd_01_00 <= CN3_addr_rd_01_00_VN; CN3_addr_rd_04_00 <= CN3_addr_rd_04_00_VN; VN1_addr_wr_01_00 <= VN1_addr_wr_01_00_VN; VN2_addr_wr_01_00 <= VN2_addr_wr_01_00_VN; VN2_addr_wr_02_00 <= VN2_addr_wr_02_00_VN; VN2_addr_wr_03_00 <= VN2_addr_wr_03_00_VN; VN2_addr_wr_04_04 <= VN2_addr_wr_04_04_VN; VN3_addr_wr_01_00 <= VN3_addr_wr_01_00_VN; VN3_addr_wr_04_00 <= VN3_addr_wr_04_00_VN; VN_wea <= VN_wea_VN; VN1_din_01_00 <= VN1_din_01_00_VN; VN1_din_02_00 <= VN1_din_02_00_VN; VN1_din_02_01 <= VN1_din_02_01_VN; VN2_din_01_00 <= VN2_din_01_00_VN; VN2_din_02_00 <= VN2_din_02_00_VN; VN2_din_03_00 <= VN2_din_03_00_VN; VN2_din_04_02 <= VN2_din_04_02_VN; VN2_din_04_03 <= VN2_din_04_03_VN; VN2_din_04_04 <= VN2_din_04_04_VN; VN3_din_01_00 <= VN3_din_01_00_VN; VN3_din_02_05 <= VN3_din_02_05_VN; VN3_din_02_06 <= VN3_din_02_06_VN; VN3_din_03_07 <= VN3_din_03_07_VN; VN3_din_03_08 <= VN3_din_03_08_VN; VN3_din_04_00 <= VN3_din_04_00_VN; DR_wea <= DR_wea_VN; DR_addr_wr <= DR_addr_wr_VN; DR_din_01 <= DR_din_01_VN; DR_din_02 <= DR_din_02_VN; DR_din_03 <= DR_din_03_VN; DR_din_04 <= DR_din_04_VN; // DR_din_05 <= DR_din_05_VN; end //******行更新模块 // 输入信号 always @(posedge clk) begin rst_CN <= rst; start_CN <= end_VN; VN1_dout_01_00_CN <= VN1_dout_01_00; VN1_dout_02_00_CN <= VN1_dout_02_00; VN1_dout_02_01_CN <= VN1_dout_02_01; VN2_dout_01_00_CN <= VN2_dout_01_00; VN2_dout_02_00_CN <= VN2_dout_02_00; VN2_dout_03_00_CN <= VN2_dout_03_00; VN2_dout_04_02_CN <= VN2_dout_04_02; VN2_dout_04_03_CN <= VN2_dout_04_03; VN2_dout_04_04_CN <= VN2_dout_04_04; VN3_dout_01_00_CN <= VN3_dout_01_00; VN3_dout_02_05_CN <= VN3_dout_02_05; VN3_dout_02_06_CN <= VN3_dout_02_06; VN3_dout_03_07_CN <= VN3_dout_03_07; VN3_dout_03_08_CN <= VN3_dout_03_08; VN3_dout_04_00_CN <= VN3_dout_04_00; end // 输出信号 // Switch_VN_CN用于指示当前处于VN更新状态（值为0）还是CN更新状态（值为1） always @(posedge clk) begin VN1_addr_wr_02_00 <= (Switch_VN_CN == 1'd1) ? VN1_addr_rd_02_00_CN : VN1_addr_wr_02_00_VN; VN1_addr_wr_02_01 <= (Switch_VN_CN == 1'd1) ? VN1_addr_rd_02_01_CN : VN1_addr_wr_02_01_VN; VN2_addr_wr_04_02 <= (Switch_VN_CN == 1'd1) ? VN2_addr_rd_04_02_CN : VN2_addr_wr_04_02_VN; VN2_addr_wr_04_03 <= (Switch_VN_CN == 1'd1) ? VN2_addr_rd_04_03_CN : VN2_addr_wr_04_03_VN; VN3_addr_wr_02_05 <= (Switch_VN_CN == 1'd1) ? VN3_addr_rd_02_05_CN : VN3_addr_wr_02_05_VN; VN3_addr_wr_02_06 <= (Switch_VN_CN == 1'd1) ? VN3_addr_rd_02_06_CN : VN3_addr_wr_02_06_VN; VN3_addr_wr_03_07 <= (Switch_VN_CN == 1'd1) ? VN3_addr_rd_03_07_CN : VN3_addr_wr_03_07_VN; VN3_addr_wr_03_08 <= (Switch_VN_CN == 1'd1) ? VN3_addr_rd_03_08_CN : VN3_addr_wr_03_08_VN; VN1_addr_rd_01_00 <= VN1_addr_rd_01_00_CN; VN2_addr_rd_01_00 <= VN2_addr_rd_01_00_CN; VN2_addr_rd_02_00 <= VN2_addr_rd_02_00_CN; VN2_addr_rd_03_00 <= VN2_addr_rd_03_00_CN; VN2_addr_rd_04_04 <= VN2_addr_rd_04_04_CN; VN3_addr_rd_01_00 <= VN3_addr_rd_01_00_CN; VN3_addr_rd_04_00 <= VN3_addr_rd_04_00_CN; CN_wea <= CN_wea_CN; CN1_addr_wr_01_00 <= CN1_addr_wr_01_00_CN; CN2_addr_wr_01_00 <= CN2_addr_wr_01_00_CN; CN2_addr_wr_02_00 <= CN2_addr_wr_02_00_CN; CN2_addr_wr_03_00 <= CN2_addr_wr_03_00_CN; CN2_addr_wr_04_04 <= CN2_addr_wr_04_04_CN; CN3_addr_wr_01_00 <= CN3_addr_wr_01_00_CN; CN3_addr_wr_04_00 <= CN3_addr_wr_04_00_CN; CN1_din_01_00 <= CN1_din_01_00_CN; CN1_din_02_00 <= CN1_din_02_00_CN; CN1_din_02_01 <= CN1_din_02_01_CN; CN2_din_01_00 <= CN2_din_01_00_CN; CN2_din_02_00 <= CN2_din_02_00_CN; CN2_din_03_00 <= CN2_din_03_00_CN; CN2_din_04_02 <= CN2_din_04_02_CN; CN2_din_04_03 <= CN2_din_04_03_CN; CN2_din_04_04 <= CN2_din_04_04_CN; CN3_din_01_00 <= CN3_din_01_00_CN; CN3_din_02_05 <= CN3_din_02_05_CN; CN3_din_02_06 <= CN3_din_02_06_CN; CN3_din_03_07 <= CN3_din_03_07_CN; CN3_din_03_08 <= CN3_din_03_08_CN; CN3_din_04_00 <= CN3_din_04_00_CN; end VN_PRO #( .MAX_ITER_NUM(MAX_ITER_NUM), .WIDTH(WIDTH) ) inst_VN_PRO ( .clk (clk), .rst_VN (rst_VN), .start_VN (start_VN), .start_frame_VN (start_frame_VN), .CHNL_dout_01 (CHNL_dout_01_VN), .CHNL_dout_02 (CHNL_dout_02_VN), .CHNL_dout_03 (CHNL_dout_03_VN), .CHNL_dout_04 (CHNL_dout_04_VN), .CN1_dout_01_00 (CN1_dout_01_00_VN), .CN1_dout_02_00 (CN1_dout_02_00_VN), .CN1_dout_02_01 (CN1_dout_02_01_VN), .CN2_dout_01_00 (CN2_dout_01_00_VN), .CN2_dout_02_00 (CN2_dout_02_00_VN), .CN2_dout_03_00 (CN2_dout_03_00_VN), .CN2_dout_04_02 (CN2_dout_04_02_VN), .CN2_dout_04_03 (CN2_dout_04_03_VN), .CN2_dout_04_04 (CN2_dout_04_04_VN), .CN3_dout_01_00 (CN3_dout_01_00_VN), .CN3_dout_02_05 (CN3_dout_02_05_VN), .CN3_dout_02_06 (CN3_dout_02_06_VN), .CN3_dout_03_07 (CN3_dout_03_07_VN), .CN3_dout_03_08 (CN3_dout_03_08_VN), .CN3_dout_04_00 (CN3_dout_04_00_VN), .ask_din (ask_din_VN), .CN1_addr_rd_01_00(CN1_addr_rd_01_00_VN), .CN1_addr_rd_02_00(CN1_addr_rd_02_00_VN), .CN1_addr_rd_02_01(CN1_addr_rd_02_01_VN), .CN2_addr_rd_01_00(CN2_addr_rd_01_00_VN), .CN2_addr_rd_02_00(CN2_addr_rd_02_00_VN), .CN2_addr_rd_03_00(CN2_addr_rd_03_00_VN), .CN2_addr_rd_04_02(CN2_addr_rd_04_02_VN), .CN2_addr_rd_04_03(CN2_addr_rd_04_03_VN), .CN2_addr_rd_04_04(CN2_addr_rd_04_04_VN), .CN3_addr_rd_01_00(CN3_addr_rd_01_00_VN), .CN3_addr_rd_02_05(CN3_addr_rd_02_05_VN), .CN3_addr_rd_02_06(CN3_addr_rd_02_06_VN), .CN3_addr_rd_03_07(CN3_addr_rd_03_07_VN), .CN3_addr_rd_03_08(CN3_addr_rd_03_08_VN), .CN3_addr_rd_04_00(CN3_addr_rd_04_00_VN), .VN_wea (VN_wea_VN), .VN1_addr_wr_01_00(VN1_addr_wr_01_00_VN), .VN1_addr_wr_02_00(VN1_addr_wr_02_00_VN), .VN1_addr_wr_02_01(VN1_addr_wr_02_01_VN), .VN2_addr_wr_01_00(VN2_addr_wr_01_00_VN), .VN2_addr_wr_02_00(VN2_addr_wr_02_00_VN), .VN2_addr_wr_03_00(VN2_addr_wr_03_00_VN), .VN2_addr_wr_04_02(VN2_addr_wr_04_02_VN), .VN2_addr_wr_04_03(VN2_addr_wr_04_03_VN), .VN2_addr_wr_04_04(VN2_addr_wr_04_04_VN), .VN3_addr_wr_01_00(VN3_addr_wr_01_00_VN), .VN3_addr_wr_02_05(VN3_addr_wr_02_05_VN), .VN3_addr_wr_02_06(VN3_addr_wr_02_06_VN), .VN3_addr_wr_03_07(VN3_addr_wr_03_07_VN), .VN3_addr_wr_03_08(VN3_addr_wr_03_08_VN), .VN3_addr_wr_04_00(VN3_addr_wr_04_00_VN), .VN1_din_01_00 (VN1_din_01_00_VN), .VN1_din_02_00 (VN1_din_02_00_VN), .VN1_din_02_01 (VN1_din_02_01_VN), .VN2_din_01_00 (VN2_din_01_00_VN), .VN2_din_02_00 (VN2_din_02_00_VN), .VN2_din_03_00 (VN2_din_03_00_VN), .VN2_din_04_02 (VN2_din_04_02_VN), .VN2_din_04_03 (VN2_din_04_03_VN), .VN2_din_04_04 (VN2_din_04_04_VN), .VN3_din_01_00 (VN3_din_01_00_VN), .VN3_din_02_05 (VN3_din_02_05_VN), .VN3_din_02_06 (VN3_din_02_06_VN), .VN3_din_03_07 (VN3_din_03_07_VN), .VN3_din_03_08 (VN3_din_03_08_VN), .VN3_din_04_00 (VN3_din_04_00_VN), .DR_wea (DR_wea_VN), .DR_addr_wr (DR_addr_wr_VN), .DR_din_01 (DR_din_01_VN), .DR_din_02 (DR_din_02_VN), .DR_din_03 (DR_din_03_VN), .DR_din_04 (DR_din_04_VN), .DR_din_05 (DR_din_05_VN), .data_start_ck_VN (data_start_ck_VN), .data_start_VN (data_start_VN), .end_VN (end_VN) ); CN_PRO #( .WIDTH(WIDTH) ) inst_CN_PRO ( .clk (clk), .rst_CN (rst_CN), .start_CN (start_CN), .VN1_dout_01_00 (VN1_dout_01_00_CN), .VN1_dout_02_00 (VN1_dout_02_00_CN), .VN1_dout_02_01 (VN1_dout_02_01_CN), .VN2_dout_01_00 (VN2_dout_01_00_CN), .VN2_dout_02_00 (VN2_dout_02_00_CN), .VN2_dout_03_00 (VN2_dout_03_00_CN), .VN2_dout_04_02 (VN2_dout_04_02_CN), .VN2_dout_04_03 (VN2_dout_04_03_CN), .VN2_dout_04_04 (VN2_dout_04_04_CN), .VN3_dout_01_00 (VN3_dout_01_00_CN), .VN3_dout_02_05 (VN3_dout_02_05_CN), .VN3_dout_02_06 (VN3_dout_02_06_CN), .VN3_dout_03_07 (VN3_dout_03_07_CN), .VN3_dout_03_08 (VN3_dout_03_08_CN), .VN3_dout_04_00 (VN3_dout_04_00_CN), .VN1_addr_rd_01_00(VN1_addr_rd_01_00_CN), .VN1_addr_rd_02_00(VN1_addr_rd_02_00_CN), .VN1_addr_rd_02_01(VN1_addr_rd_02_01_CN), .VN2_addr_rd_01_00(VN2_addr_rd_01_00_CN), .VN2_addr_rd_02_00(VN2_addr_rd_02_00_CN), .VN2_addr_rd_03_00(VN2_addr_rd_03_00_CN), .VN2_addr_rd_04_02(VN2_addr_rd_04_02_CN), .VN2_addr_rd_04_03(VN2_addr_rd_04_03_CN), .VN2_addr_rd_04_04(VN2_addr_rd_04_04_CN), .VN3_addr_rd_01_00(VN3_addr_rd_01_00_CN), .VN3_addr_rd_02_05(VN3_addr_rd_02_05_CN), .VN3_addr_rd_02_06(VN3_addr_rd_02_06_CN), .VN3_addr_rd_03_07(VN3_addr_rd_03_07_CN), .VN3_addr_rd_03_08(VN3_addr_rd_03_08_CN), .VN3_addr_rd_04_00(VN3_addr_rd_04_00_CN), .CN_wea (CN_wea_CN), .CN1_addr_wr_01_00(CN1_addr_wr_01_00_CN), .CN1_addr_wr_02_00(CN1_addr_wr_02_00_CN), .CN1_addr_wr_02_01(CN1_addr_wr_02_01_CN), .CN2_addr_wr_01_00(CN2_addr_wr_01_00_CN), .CN2_addr_wr_02_00(CN2_addr_wr_02_00_CN), .CN2_addr_wr_03_00(CN2_addr_wr_03_00_CN), .CN2_addr_wr_04_02(CN2_addr_wr_04_02_CN), .CN2_addr_wr_04_03(CN2_addr_wr_04_03_CN), .CN2_addr_wr_04_04(CN2_addr_wr_04_04_CN), .CN3_addr_wr_01_00(CN3_addr_wr_01_00_CN), .CN3_addr_wr_02_05(CN3_addr_wr_02_05_CN), .CN3_addr_wr_02_06(CN3_addr_wr_02_06_CN), .CN3_addr_wr_03_07(CN3_addr_wr_03_07_CN), .CN3_addr_wr_03_08(CN3_addr_wr_03_08_CN), .CN3_addr_wr_04_00(CN3_addr_wr_04_00_CN), .CN1_din_01_00 (CN1_din_01_00_CN), .CN1_din_02_00 (CN1_din_02_00_CN), .CN1_din_02_01 (CN1_din_02_01_CN), .CN2_din_01_00 (CN2_din_01_00_CN), .CN2_din_02_00 (CN2_din_02_00_CN), .CN2_din_03_00 (CN2_din_03_00_CN), .CN2_din_04_02 (CN2_din_04_02_CN), .CN2_din_04_03 (CN2_din_04_03_CN), .CN2_din_04_04 (CN2_din_04_04_CN), .CN3_din_01_00 (CN3_din_01_00_CN), .CN3_din_02_05 (CN3_din_02_05_CN), .CN3_din_02_06 (CN3_din_02_06_CN), .CN3_din_03_07 (CN3_din_03_07_CN), .CN3_din_03_08 (CN3_din_03_08_CN), .CN3_din_04_00 (CN3_din_04_00_CN), .end_CN (end_CN) ); //******译码结果校验模块 // 输入信号 reg rst_CK = 1'd0; reg start_CK = 1'd0; reg nd_CK = 1'd0; reg DR_din_01_CK = 1'd0; reg DR_din_02_CK = 1'd0; reg DR_din_03_CK = 1'd0; reg DR_din_04_CK = 1'd0; reg DR_din_05_CK = 1'd0; always @(posedge clk) begin rst_CK <= rst; start_CK <= data_start_ck_VN; nd_CK <= DR_wea_VN; DR_din_01_CK <= DR_din_01_VN; DR_din_02_CK <= DR_din_02_VN; DR_din_03_CK <= DR_din_03_VN; DR_din_04_CK <= DR_din_04_VN; DR_din_05_CK <= DR_din_05_VN; end // 输出信号 wire [8:0] gd_frames_CK; wire [8:0] bd_frames_CK; wire [8:0] tl_frames_CK; always @(posedge clk) begin gd_frames <= gd_frames_CK; bd_frames <= bd_frames_CK; tl_frames <= tl_frames_CK; end CK_PRO inst_CK_PRO ( .clk (clk), .rst_OUTCK (rst_CK), .start_OUTCK(start_CK), .nd_OUTCK (nd_CK), .DR_din_01 (DR_din_01_CK), .DR_din_02 (DR_din_02_CK), .DR_din_03 (DR_din_03_CK), .DR_din_04 (DR_din_04_CK), .DR_din_05 (DR_din_05_CK), .gd_frames (gd_frames_CK), .bd_frames (bd_frames_CK), .tl_frames (tl_frames_CK) ); //******译码结果输出模块 // 输入信号 reg start_OUT = 1'd0; reg rst_OUT = 1'd0; reg DR_dout_01_OUT = 1'd0; reg DR_dout_02_OUT = 1'd0; reg DR_dout_03_OUT = 1'd0; reg DR_dout_04_OUT = 1'd0; always @(posedge clk) begin start_OUT <= data_start_VN; rst_OUT <= rst; DR_dout_01_OUT <= DR_dout_01; DR_dout_02_OUT <= DR_dout_02; DR_dout_03_OUT <= DR_dout_03; DR_dout_04_OUT <= DR_dout_04; end // 输出信号 wire ldpc_syncout_OUT; wire rdy_OUT; wire ldpc_dout_OUT; wire [8:0] DR_addr_rd_01_OUT; wire [8:0] DR_addr_rd_02_OUT; wire [8:0] DR_addr_rd_03_OUT; wire [8:0] DR_addr_rd_04_OUT; always @(posedge clk) begin DR_addr_rd_01 <= DR_addr_rd_01_OUT; DR_addr_rd_02 <= DR_addr_rd_02_OUT; DR_addr_rd_03 <= DR_addr_rd_03_OUT; DR_addr_rd_04 <= DR_addr_rd_04_OUT; ldpc_syncout <= ldpc_syncout_OUT; rdy <= rdy_OUT; ldpc_dout <= ldpc_dout_OUT; ask_din <= ask_din_VN; end OUT_PRO #( .OUT_ONLY_INFORMATION(OUT_ONLY_INFORMATION) ) inst_OUT_PRO ( .clk (clk), .rst_OUT (rst_OUT), .start_OUT (start_OUT), .DR_dout_01 (DR_dout_01_OUT), .DR_dout_02 (DR_dout_02_OUT), .DR_dout_03 (DR_dout_03_OUT), .DR_dout_04 (DR_dout_04_OUT), .DR_addr_rd_01 (DR_addr_rd_01_OUT), .DR_addr_rd_02 (DR_addr_rd_02_OUT), .DR_addr_rd_03 (DR_addr_rd_03_OUT), .DR_addr_rd_04 (DR_addr_rd_04_OUT), .ldpc_syncout_OUT(ldpc_syncout_OUT), .rdy_OUT (rdy_OUT), .ldpc_dout_OUT (ldpc_dout_OUT) ); //******校验节点信息存储RAM // H阵第1行 RAM_512X1_8 RAM_CN_01 ( .clka (clk), .wea (CN_wea), .addra(CN1_addr_wr_01_00), .dina (CN1_din_01_00), .clkb (clk), .addrb(CN1_addr_rd_01_00), .doutb(CN1_dout_01_00) ); RAM_512X2_8 RAM_CN_02 ( .clka (clk), .wea (CN_wea), .addra(CN1_addr_wr_02_00), .dina (CN1_din_02_00), .douta(CN1_dout_02_00), .clkb (clk), .web (CN_wea), .addrb(CN1_addr_wr_02_01), .dinb (CN1_din_02_01), .doutb(CN1_dout_02_01) ); // H阵第2行 RAM_512X1_8 RAM_CN_03 ( .clka (clk), .wea (CN_wea), .addra(CN2_addr_wr_01_00), .dina (CN2_din_01_00), .clkb (clk), .addrb(CN2_addr_rd_01_00), .doutb(CN2_dout_01_00) ); RAM_512X1_8 RAM_CN_04 ( .clka (clk), .wea (CN_wea), .addra(CN2_addr_wr_02_00), .dina (CN2_din_02_00), .clkb (clk), .addrb(CN2_addr_rd_02_00), .doutb(CN2_dout_02_00) ); RAM_512X1_8 RAM_CN_05 ( .clka (clk), .wea (CN_wea), .addra(CN2_addr_wr_03_00), .dina (CN2_din_03_00), .clkb (clk), .addrb(CN2_addr_rd_03_00), .doutb(CN2_dout_03_00) ); RAM_512X2_8 RAM_CN_06 ( .clka (clk), .wea (CN_wea), .addra(CN2_addr_wr_04_02), .dina (CN2_din_04_02), .douta(CN2_dout_04_02), .clkb (clk), .web (CN_wea), .addrb(CN2_addr_wr_04_03), .dinb (CN2_din_04_03), .doutb(CN2_dout_04_03) ); RAM_512X1_8 RAM_CN_07 ( .clka (clk), .wea (CN_wea), .addra(CN2_addr_wr_04_04), .dina (CN2_din_04_04), .clkb (clk), .addrb(CN2_addr_rd_04_04), .doutb(CN2_dout_04_04) ); // H阵第3行 RAM_512X1_8 RAM_CN_08 ( .clka (clk), .wea (CN_wea), .addra(CN3_addr_wr_01_00), .dina (CN3_din_01_00), .clkb (clk), .addrb(CN3_addr_rd_01_00), .doutb(CN3_dout_01_00) ); RAM_512X2_8 RAM_CN_09 ( .clka (clk), .wea (CN_wea), .addra(CN3_addr_wr_02_05), .dina (CN3_din_02_05), .douta(CN3_dout_02_05), .clkb (clk), .web (CN_wea), .addrb(CN3_addr_wr_02_06), .dinb (CN3_din_02_06), .doutb(CN3_dout_02_06) ); RAM_512X2_8 RAM_CN_10 ( .clka (clk), .wea (CN_wea), .addra(CN3_addr_wr_03_07), .dina (CN3_din_03_07), .douta(CN3_dout_03_07), .clkb (clk), .web (CN_wea), .addrb(CN3_addr_wr_03_08), .dinb (CN3_din_03_08), .doutb(CN3_dout_03_08) ); RAM_512X1_8 RAM_CN_11 ( .clka (clk), .wea (CN_wea), .addra(CN3_addr_wr_04_00), .dina (CN3_din_04_00), .clkb (clk), .addrb(CN3_addr_rd_04_00), .doutb(CN3_dout_04_00) ); //******变量节点信息存储RAM // H阵第1行，注意H阵第1行第3列不进行列VN的列更新 RAM_512X1_8 RAM_VN_01 ( .clka (clk), .wea (VN_wea), .addra(VN1_addr_wr_01_00), .dina (VN1_din_01_00), .clkb (clk), .addrb(VN1_addr_rd_01_00), .doutb(VN1_dout_01_00) ); RAM_512X2_8 RAM_VN_02 ( .clka (clk), .wea (VN_wea), .addra(VN1_addr_wr_02_00), .dina (VN1_din_02_00), .douta(VN1_dout_02_00), .clkb (clk), .web (VN_wea), .addrb(VN1_addr_wr_02_01), .dinb (VN1_din_02_01), .doutb(VN1_dout_02_01) ); // H阵第2行 RAM_512X1_8 RAM_VN_03 ( .clka (clk), .wea (VN_wea), .addra(VN2_addr_wr_01_00), .dina (VN2_din_01_00), .clkb (clk), .addrb(VN2_addr_rd_01_00), .doutb(VN2_dout_01_00) ); RAM_512X1_8 RAM_VN_04 ( .clka (clk), .wea (VN_wea), .addra(VN2_addr_wr_02_00), .dina (VN2_din_02_00), .clkb (clk), .addrb(VN2_addr_rd_02_00), .doutb(VN2_dout_02_00) ); RAM_512X1_8 RAM_VN_05 ( .clka (clk), .wea (VN_wea), .addra(VN2_addr_wr_03_00), .dina (VN2_din_03_00), .clkb (clk), .addrb(VN2_addr_rd_03_00), .doutb(VN2_dout_03_00) ); RAM_512X2_8 RAM_VN_06 ( .clka (clk), .wea (VN_wea), .addra(VN2_addr_wr_04_02), .dina (VN2_din_04_02), .douta(VN2_dout_04_02), .clkb (clk), .web (VN_wea), .addrb(VN2_addr_wr_04_03), .dinb (VN2_din_04_03), .doutb(VN2_dout_04_03) ); RAM_512X1_8 RAM_VN_07 ( .clka (clk), .wea (VN_wea), .addra(VN2_addr_wr_04_04), .dina (VN2_din_04_04), .clkb (clk), .addrb(VN2_addr_rd_04_04), .doutb(VN2_dout_04_04) ); // H阵第3行 RAM_512X1_8 RAM_VN_08 ( .clka (clk), .wea (VN_wea), .addra(VN3_addr_wr_01_00), .dina (VN3_din_01_00), .clkb (clk), .addrb(VN3_addr_rd_01_00), .doutb(VN3_dout_01_00) ); RAM_512X2_8 RAM_VN_09 ( .clka (clk), .wea (VN_wea), .addra(VN3_addr_wr_02_05), .dina (VN3_din_02_05), .douta(VN3_dout_02_05), .clkb (clk), .web (VN_wea), .addrb(VN3_addr_wr_02_06), .dinb (VN3_din_02_06), .doutb(VN3_dout_02_06) ); RAM_512X2_8 RAM_VN_10 ( .clka (clk), .wea (VN_wea), .addra(VN3_addr_wr_03_07), .dina (VN3_din_03_07), .douta(VN3_dout_03_07), .clkb (clk), .web (VN_wea), .addrb(VN3_addr_wr_03_08), .dinb (VN3_din_03_08), .doutb(VN3_dout_03_08) ); RAM_512X1_8 RAM_VN_11 ( .clka (clk), .wea (VN_wea), .addra(VN3_addr_wr_04_00), .dina (VN3_din_04_00), .clkb (clk), .addrb(VN3_addr_rd_04_00), .doutb(VN3_dout_04_00) ); //******判决结果信息存储RAM //注意：对于码率为1/2的CCSDS码而言，真正的码字存储在RAM_DR_01~RAM_DR_04中，RAM_DR_05只是在验证HC’==0时用。 RAM_512_1 RAM_DR_01 ( .clka (clk), .wea (DR_wea), .addra(DR_addr_wr), .dina (DR_din_01), .clkb (clk), .addrb(DR_addr_rd_01), .doutb(DR_dout_01) ); RAM_512_1 RAM_DR_02 ( .clka (clk), .wea (DR_wea), .addra(DR_addr_wr), .dina (DR_din_02), .clkb (clk), .addrb(DR_addr_rd_02), .doutb(DR_dout_02) ); RAM_512_1 RAM_DR_03 ( .clka (clk), .wea (DR_wea), .addra(DR_addr_wr), .dina (DR_din_03), .clkb (clk), .addrb(DR_addr_rd_03), .doutb(DR_dout_03) ); RAM_512_1 RAM_DR_04 ( .clka (clk), .wea (DR_wea), .addra(DR_addr_wr), .dina (DR_din_04), .clkb (clk), .addrb(DR_addr_rd_04), .doutb(DR_dout_04) ); // RAM_512_1 RAM_DR_05 (.clka(clk),.wea(DR_wea),.addra(DR_addr_wr),.dina(DR_din_05),.clkb(clk),.addrb(DR_addr_rd_05),.doutb(DR_dout_05)); endmodule