// * Engineer: 
// * *************************************************** *
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// * *************************************************** *
// * Update Date: 
// * NOTE       : 
module scrambler #(
    parameter ILA_ON = 0
) (
    input             clk,
    input             rst_n,
    // s_axis_stream
    input      [31:0] s_axis_tdata,
    input             s_axis_tvalid,
    output reg        s_axis_tready,
    input             s_axis_tlast,
    input      [31:0] s_axis_rd_data_count,
    // m_axis_stream
    output reg [31:0] m_axis_tdata,
    output reg        m_axis_tvalid,
    input             m_axis_tready,
    output reg        m_axis_tlast
);


    // ******** Wire & Reg  ********

    wire        rst;

    reg  [ 2:0] addr_scramble = 0;
    reg  [ 2:0] addr_scramble_d1 = 0;
    reg  [ 2:0] addr_scramble_d2 = 0;
    wire [31:0] data_scramble_mask;
    reg  [ 3:0] cnt_in;

    reg  [31:0] s_axis_tdata_d1;
    reg  [31:0] s_axis_tdata_d2;

    reg         s_axis_tready_d1;
    reg         s_axis_tlast_d1;
    // fsm
    reg  [ 1:0] cs = 0;
    reg  [ 1:0] ns = 0;
    localparam S_IDLE = 0;
    localparam S_WORKING = 1;


    // ******** Assingment  ********

    assign rst = ~rst_n;

    // ******** Logic Block ********

    always @(posedge clk) begin
        cs <= ns;
    end

    always @(*) begin
        ns = cs;
        case (cs)
            S_IDLE: begin
                if (s_axis_tvalid && m_axis_tready && s_axis_rd_data_count >= 8) begin
                    ns = S_WORKING;
                end
            end
            S_WORKING: begin
                if (addr_scramble_d2 == 3'h7) begin
                    ns = S_IDLE;
                end
            end
            default: begin
                ns = S_IDLE;
            end
        endcase
    end

    always @(posedge clk) begin
        if (cs == S_IDLE) begin
            addr_scramble <= 0;
        end
        else begin
            addr_scramble <= addr_scramble + 1;
        end
        addr_scramble_d1 <= addr_scramble;
        addr_scramble_d2 <= addr_scramble_d1;
    end

    always @(posedge clk) begin
        if (cs == S_WORKING) begin
            m_axis_tdata <= s_axis_tdata_d1 ^ data_scramble_mask;
        end
        else begin
            m_axis_tdata <= 0;
        end
    end

    always @(posedge clk) begin
        if (cs == S_WORKING && s_axis_tvalid && cnt_in < 4'd8) begin
            s_axis_tready <= 1;
        end
        else begin
            s_axis_tready <= 0;
        end
    end


    always @(posedge clk) begin
        s_axis_tdata_d1  <= s_axis_tdata;

        s_axis_tready_d1 <= s_axis_tready;
        m_axis_tvalid    <= s_axis_tready_d1;

        s_axis_tlast_d1  <= s_axis_tlast;
        m_axis_tlast     <= s_axis_tlast_d1;

    end

    always @(posedge clk) begin
        if (cs == S_IDLE) begin
            cnt_in <= 0;
        end
        else if (cs == S_WORKING && cnt_in < 4'd8) begin
            cnt_in <= cnt_in + 1;
        end
    end


    // ********    Inst     ********

    bram_scramble u_bram_scramble (
        .clka (clk),                // input wire clka
        .addra(addr_scramble),      // input wire [2 : 0] addra
        .douta(data_scramble_mask)  // output wire [31 : 0] douta
    );

    // ********    Debug    ********

    generate
        if (ILA_ON)
            ila_scrambler u_ila_scrambler (
                .clk   (clk),                // input wire clk
                .probe0(s_axis_tvalid),      // input wire [0:0]  probe0  
                .probe1(s_axis_tready),      // input wire [0:0]  probe1 
                .probe2(s_axis_tdata),       // input wire [31:0]  probe2 
                .probe3(s_axis_tlast),       // input wire [0:0]  probe3 
                .probe4(m_axis_tvalid),      // input wire [0:0]  probe4 
                .probe5(m_axis_tready),      // input wire [0:0]  probe5 
                .probe6(m_axis_tdata),       // input wire [31:0]  probe6 
                .probe7(m_axis_tlast),       // input wire [0:0]  probe7 
                .probe8(data_scramble_mask)  // input wire [31:0]  probe8
            );

    endgenerate


endmodule