`timescale 1ns / 1ns
module tb_scrambler ();


    reg clk = 0;
    always #1 clk <= ~clk;
    reg [3:0] cnt_startup = 0;
    reg       rst;

    always @(posedge clk) begin
        if (cnt_startup < 4'hF) begin
            cnt_startup <= cnt_startup + 1;
        end
        rst <= cnt_startup <= 4'hC;
    end


    reg  [31:0] s_axis_tdata;
    reg         s_axis_tvalid;
    wire        s_axis_tready;
    reg         s_axis_tlast;
    wire [31:0] m_axis_tdata;
    wire        m_axis_tvalid;
    // wire        m_axis_tvalid;
    wire        m_axis_tlast;
    reg  [31:0] cnt = 0;

    always @(posedge clk) begin
        s_axis_tvalid <= (cnt_startup == 4'hF && cnt < 32);
        if (rst) begin
            s_axis_tdata <= 0;
        end
        else if (s_axis_tready && cnt < 32) begin
            s_axis_tdata <= cnt;
            cnt          <= cnt + 1;
        end
    end

    scrambler u_scrambler (
        .clk          (clk),
        .rst          (rst),
        .s_axis_tdata (s_axis_tdata),
        .s_axis_tvalid(s_axis_tvalid),
        .s_axis_tready(s_axis_tready),
        .s_axis_tlast (s_axis_tlast),
        .m_axis_tdata (m_axis_tdata),
        .m_axis_tvalid(m_axis_tvalid),
        .m_axis_tready(1),
        .m_axis_tlast (m_axis_tlast)
    );


endmodule