`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:27:25 01/18/2018 
// Design Name: 
// Module Name:    Normalization_Factor_0_8125 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Normalization_Factor_0_8125 #(
    parameter WIDTH = 4'd8
) (
    input                  clk,
    input      [WIDTH-1:0] din_NF,         //输入为非负数
    output reg [WIDTH-1:0] dout_NF = 8'd0  //输出相对输入延时3个时钟周期
);

    reg [WIDTH-1:0] din_NF_reg0 = 8'd0, din_NF_reg1 = 8'd0;
    reg [WIDTH-1:0] sum_1 = 8'd0, sum_2 = 8'd0;
    always @(posedge clk) begin
        din_NF_reg0 <= din_NF;
        din_NF_reg1 <= din_NF_reg0;
    end
    always @(posedge clk) begin  //对输入数据乘以系数0.8125
        sum_1 <= (din_NF >> 1) + (din_NF >> 2);
        sum_2 <= sum_1 + (din_NF_reg0 >> 4);
        case ({
            din_NF_reg1[3:0]
        })  //matlab中用round函数，verilog中默认是floor函数
            4'b0000: dout_NF <= sum_2 + 8'd0;
            4'b0001: dout_NF <= sum_2 + 8'd1;
            4'b0010: dout_NF <= sum_2 + 8'd1;
            4'b0011: dout_NF <= sum_2 + 8'd1;
            4'b0100: dout_NF <= sum_2 + 8'd0;
            4'b0101: dout_NF <= sum_2 + 8'd1;
            4'b0110: dout_NF <= sum_2 + 8'd1;  //32个数，0~15和16~31的数是一样的，所以用din_NF_reg1&4'b1111，		                                         
            4'b0111: dout_NF <= sum_2 + 8'd2;  //例如，din_NF_reg1=6'd19,经过din_NF_reg1&4'b1111之后，变成了6'd3
            4'b1000: dout_NF <= sum_2 + 8'd1;
            4'b1001: dout_NF <= sum_2 + 8'd1;
            4'b1010: dout_NF <= sum_2 + 8'd1;
            4'b1011: dout_NF <= sum_2 + 8'd2;
            4'b1100: dout_NF <= sum_2 + 8'd1;
            4'b1101: dout_NF <= sum_2 + 8'd2;
            4'b1110: dout_NF <= sum_2 + 8'd1;
            4'b1111: dout_NF <= sum_2 + 8'd2;
            default: dout_NF <= 8'd0;
        endcase
    end
endmodule