`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/11/14 16:20:11
// Design Name: 
// Module Name: ad9361_spi_interface
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module ad9361_spi_interface (
    input            ad9361_spi_miso,
    output           ad9361_spi_csn,
    output           ad9361_spi_clk,
    output           ad9361_spi_mosi,
    // spi interface
    input            spi_sclk,
    input      [1:0] spi_cs,
    output reg       spi_sdi,
    input            spi_sdo,
    input            spi_sdo_t,
    input            spi_three_wire,
    input            spi_active
);

    // ad9361 - three-wire spi or four-wire spi
    assign ad9361_spi_clk  = spi_sclk;
    assign ad9361_spi_csn  = spi_cs[1];
    assign ad9361_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;

    // select sdi signal
    always @(*) begin
        if (~ad9361_spi_csn) spi_sdi = spi_three_wire ? ad9361_spi_mosi : ad9361_spi_miso;
        else spi_sdi = 1'bz;
    end




endmodule