`timescale 1ns / 1ns
// * Engineer: 
// * *************************************************** *
// * ███████╗ ██████╗ ██████╗  ██████╗  ██████╗ ██╗  ██╗ *
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// * *************************************************** *
// * Create Date: 2024/04/08
// * Update Date: 2024/05/17

// ! PLEASE MAKE SURE THE PARAMETER ARE VALID 
// ! WHEN U INSTANTIATE THIS MODULE
module tdma #(
    parameter SLOT_LEN = 1250000,
    parameter TIC_TO_PS_LEN = 1200000,
    parameter TIC_FRAME_SYNC = 42272
) (
                        input  clk,
                        input  rst,
                        input  flag_is_master,   // TODO: refactor it to parameters
                        input  flag_frame_sync,
                        output intr_2ps,
    (* KEEP = "TRUE" *) output tx_start,
    (* KEEP = "TRUE" *) output rx_rst
);

    // TODO: 需要检查综合后电路是否会被优化
    // BUG: 需要修复bug，重构代码，把主从分开写，通过参数进行优化
    // ******** Wire & Reg  ********
    reg        flag_is_tx_slot;
    // ******** Assingment  ********

    // ******** Logic Block ********


    reg [23:0] cnt; 
    always @(posedge clk) begin
        if (rst) begin
            cnt <= 0;
        end
        else begin
            if (!flag_is_master && flag_frame_sync) begin
                // slave update cnt
                cnt <= TIC_FRAME_SYNC;
            end
            else begin
                // master
                if (cnt < SLOT_LEN) begin
                    cnt <= cnt + 1;
                end
                else begin
                    cnt <= 0;
                end
            end
        end
    end
    assign tx_start = flag_is_tx_slot & (cnt == 16'd10);
    assign rx_rst   = flag_is_tx_slot | (~flag_is_tx_slot & (cnt <= 16'd10));
    assign intr_2ps = ~flag_is_tx_slot & (cnt == TIC_TO_PS_LEN);

    always @(posedge clk) begin
        if (rst) begin
            flag_is_tx_slot <= 0;
        end
        else if (!flag_is_master && flag_frame_sync) begin
            flag_is_tx_slot <= 0;
        end
        else if (cnt == 16'd1) begin
            flag_is_tx_slot <= ~flag_is_tx_slot;
        end
    end



    // ********    Inst     ********

    // ********    Debug    ********

endmodule