`timescale 1ns / 1ps
// * Engineer: 
// * *************************************************** *
// * ███████╗ ██████╗ ██████╗  ██████╗  ██████╗ ██╗  ██╗ *
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// * *************************************************** *
// * Update Date: 
// * NOTE       : this is the first version convert from wider bitwidth to narrower bitwidth 

module width_convert #(
    parameter INPUT_WIDTH  = 16,
    parameter OUTPUT_WIDTH = 2
) (
    input                             clk,
    input                             rst,
    input                             data_in_valid,
    input  wire                       data_in_ready,
    input  wire [INPUT_WIDTH - 1 : 0] data_in,
    output reg                        data_out_valid,
    output reg  [OUTPUT_WIDTH -1 : 0] data_out

);

    localparam CNT_MAX = INPUT_WIDTH / OUTPUT_WIDTH;

    // ******** Wire & Reg  ********

    reg [        INPUT_WIDTH-1:0] data_in_latch;
    reg [$clog2(CNT_MAX) - 1 : 0] cnt;
    reg                           flag_working;



    // ******** Assingment  ********

    assign data_in_ready = (~flag_working & ~rst) | (cnt == CNT_MAX - 1);

    // ******** Logic Block ********

    always @(posedge clk) begin
        if (rst) begin
            data_in_latch <= 'd0;
        end
        else begin
            if (data_in_valid && data_in_ready) begin
                data_in_latch <= data_in;
            end
        end
    end

    always @(posedge clk) begin
        if (rst) begin
            flag_working <= 0;
        end
        else if (data_in_valid) begin
            flag_working <= 1;
        end
        else if (cnt == CNT_MAX - 1) begin
            flag_working <= 0;
        end
    end

    always @(posedge clk) begin
        if (rst) begin
            cnt <= 0;
        end
        else if (flag_working) begin
            cnt <= cnt + 1;
        end
    end

    always @(*) begin
        data_out       = data_in_latch[cnt*OUTPUT_WIDTH+OUTPUT_WIDTH-1-:OUTPUT_WIDTH];
        data_out_valid = flag_working;
    end
    // ********    Inst     ********

    // ********    Debug    ********







endmodule