`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 2024/04/15 20:17:12 // Design Name: // Module Name: tb_Receiver // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module tb_Receiver (); reg clk; reg clk_2x; reg clk_4x; reg rst; localparam CLK_PERIOD = 20_0; always #(10) clk = ~clk; always #(5) clk_2x = ~clk_2x; always #(2.5) clk_4x = ~clk_4x; // * start reg [11:0] ad9361_rx_data_i; reg [11:0] ad9361_rx_data_q; reg flag; reg [11:0] mem_i [10000:0]; reg [11:0] mem_q [10000:0]; initial begin clk <= 1'b0; clk_2x <= 1'b0; clk_4x <= 1'b0; $readmemb("D:/WorkSpace/IC/SIP/ToLYY/ToLYY/MM20/MM20.srcs/sim_1/new/ad9361_i_testbench.txt", mem_i); $readmemb("D:/WorkSpace/IC/SIP/ToLYY/ToLYY/MM20/MM20.srcs/sim_1/new/ad9361_q_testbench.txt", mem_q); rst <= 1'b0; flag <= 0; #(CLK_PERIOD * 50) rst <= 1; #(CLK_PERIOD * 10) rst <= 0; #(CLK_PERIOD * 100) flag <= 1; end Receiver u_Receiver ( .clk (clk), .clk_2x (clk_2x), .clk_4x (clk_4x), .rst (rst), .speed_mode (3'd0), .ad9361_rx_data_i(ad9361_rx_data_i), .ad9361_rx_data_q(ad9361_rx_data_q) ); reg [15:0] index = 16'd0; always @(posedge clk) begin if (rst) begin index <= 'd0; ad9361_rx_data_i <= 'd0; ad9361_rx_data_q <= 'd0; end else if (flag) begin ad9361_rx_data_i <= mem_i[index]; ad9361_rx_data_q <= mem_q[index]; index <= index + 16'd1; end end endmodule