`timescale 1ns / 1ps module tb_width_convert (); reg clk = 1; reg rst = 1; always #(2) clk <= ~clk; initial begin #10 rst <= 1'b0; end reg [31:0] data_in; reg data_in_valid; wire data_in_ready; wire data_out_valid; wire [ 0:0] data_out; width_convert #( .INPUT_WIDTH (32), .OUTPUT_WIDTH(1) ) u_width_convert ( .clk (clk), .rst (rst), .data_in_valid (data_in_valid), .data_in_ready (data_in_ready), .data_in (data_in), .data_out_valid(data_out_valid), .data_out (data_out) ); reg [5:0] cnt_startup; reg [3:0] cnt_data_in; always @(posedge clk) begin if (rst) begin cnt_startup <= 0; end else if (cnt_startup < 6'b111111) begin cnt_startup <= cnt_startup + 1; end end reg [5:0] cnt_in; localparam CNT_IN_MAX = 32; always @(posedge clk) begin if (rst) begin cnt_in <= 0; end else if (cnt_in == CNT_IN_MAX) begin cnt_in <= 0; end else begin cnt_in <= cnt_in + 1; end end always @(posedge clk) begin if (rst) begin data_in <= $random(); cnt_data_in <= 0; end else if (cnt_startup == 6'b111111 && cnt_in == CNT_IN_MAX && cnt_data_in < 5) begin data_in <= $random(); cnt_data_in <= cnt_data_in + 1; end end always @(posedge clk) begin // if (cnt_startup == 6'b111111 && cnt_in == CNT_IN_MAX) begin // data_in_valid <= 1; // end // else begin // data_in_valid <= 0; // end if (rst) begin data_in_valid <= 0; end else if (cnt_startup == 6'b111_111 && cnt_data_in < 5) begin data_in_valid <= 1; end else begin data_in_valid <= 0; end end endmodule