`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/11/18 21:06:38
// Design Name: 
// Module Name: Interp_half
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Interp_half(
	input clk,
	input [9:0] din_p1,
	input [9:0] din_t0,
	input [9:0] din_n1,
	input [9:0] din_n2,
	
	output reg [9:0] dout

    );
	
	wire [13:0] multquartert0;
	wire [13:0] multquartern1;
	CN1_half CT0_half (.CLK(clk), .A(din_t0), .P(multquartert0));	
	CN1_half CN1_half (.CLK(clk), .A(din_n1), .P(multquartern1));	
	
	reg [9:0] multquarterp1 = 10'd0;
	reg [9:0] multquartern2 = 10'd0;
	always @(posedge clk)begin
		multquarterp1 <= din_p1;
		multquartern2 <= din_n2;
	end

	reg [14:0] sumquarter1 = 15'd0;
	reg [14:0] sumquarter2 = 15'd0;
	always @(posedge clk)begin
		sumquarter1 <= {multquartert0[13],multquartert0}-{{5{multquarterp1[9]}},multquarterp1};
		sumquarter2 <= {multquartern1[13],multquartern1}-{{5{multquartern2[9]}},multquartern2};
	end
	
	
	reg [15:0] sumquarter3 = 16'd0;
	always @(posedge clk)begin
		sumquarter3 <= {sumquarter2[14],sumquarter2}+{sumquarter1[14],sumquarter1};		
	end
	
	
	always @(posedge clk)begin
		if(sumquarter3[15:13]==3'b111||sumquarter3[15:13]==3'b000)begin
			dout <= sumquarter3[13:4];	
		end else begin
			dout	<=	(sumquarter3[15]==1'b1) ? 10'b10_0000_0000	:	10'b01_1111_1111;
		end
	end	
		
	

endmodule