`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:   17:44 11/14/2019
// Design Name:
// Module Name:    MF_Top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MF_Top (
    input clk,
    input rst,

    input [11:0] dini,
    input [11:0] dinq,
    input        start,

    output reg [9:0] matchfilterout_i = 10'd0,
    output reg [9:0] matchfilterout_q = 10'd0,
    output reg       MF_rdy,
    output reg       MF_rst
);

    wire        s_axis_data_tvalid_i;
    wire        s_axis_data_tready_i;
    wire        m_axis_data_tvalid_i;
    wire [31:0] MF_m_axis_data_tdata_i;

    assign s_axis_data_tvalid_i = start;
    MF12p5_12bit MF12p5_12bit_i (
        .aclk              (clk),                    // input wire aclk
        .s_axis_data_tvalid(s_axis_data_tvalid_i),   // input wire s_axis_data_tvalid
        .s_axis_data_tready(s_axis_data_tready_i),   // output wire s_axis_data_tready
        .s_axis_data_tdata ({4'd0, dini}),           // input wire [15 : 0] s_axis_data_tdata
        .m_axis_data_tvalid(m_axis_data_tvalid_i),   // output wire m_axis_data_tvalid
        .m_axis_data_tdata (MF_m_axis_data_tdata_i)  // output wire [31 : 0] m_axis_data_tdata
    );

    wire        s_axis_data_tvalid_q;
    wire        s_axis_data_tready_q;
    wire        m_axis_data_tvalid_q;
    wire [31:0] MF_m_axis_data_tdata_q;

    assign s_axis_data_tvalid_q = start;
    MF12p5_12bit MF12p5_12bit_q (
        .aclk              (clk),                    // input wire aclk
        .s_axis_data_tvalid(s_axis_data_tvalid_q),   // input wire s_axis_data_tvalid
        .s_axis_data_tready(s_axis_data_tready_q),   // output wire s_axis_data_tready
        .s_axis_data_tdata ({4'd0, dinq}),           // input wire [15 : 0] s_axis_data_tdata
        .m_axis_data_tvalid(m_axis_data_tvalid_q),   // output wire m_axis_data_tvalid
        .m_axis_data_tdata (MF_m_axis_data_tdata_q)  // output wire [31 : 0] m_axis_data_tdata
    );

    //截位：结果为MF_m_axis_data_tdata_i/q[25:0]
    //低位截位15bit，高位截位1bit，得10bit宽结果
    always @(posedge clk) begin
        if (MF_m_axis_data_tdata_i[25:24] == 2'b00 || MF_m_axis_data_tdata_i[25:24] == 2'b11) begin
            matchfilterout_i <= MF_m_axis_data_tdata_i[24:15];
        end
        else begin
            matchfilterout_i <= (MF_m_axis_data_tdata_i[25] == 1'b1) ? 10'b10_0000_0000 : 10'b01_1111_1111;
        end

        if (MF_m_axis_data_tdata_q[25:24] == 2'b00 || MF_m_axis_data_tdata_q[25:24] == 2'b11) begin
            matchfilterout_q <= MF_m_axis_data_tdata_q[24:15];
        end
        else begin
            matchfilterout_q <= (MF_m_axis_data_tdata_q[25] == 1'b1) ? 10'b10_0000_0000 : 10'b01_1111_1111;
        end
    end

    reg MF_rdy_d1;
    always @(posedge clk) begin
        MF_rdy_d1 <= MF_rdy;
        if (rst) begin
            MF_rdy <= 1'b0;
            MF_rst <= 1'b0;
        end
        else begin
            MF_rdy <= start;
            if ((MF_rdy == 1'b1) && (MF_rdy_d1 == 1'b0)) begin
                MF_rst <= 1'b1;
            end
            else begin
                MF_rst <= 1'b0;
            end
        end
    end

    //------DEBUG模块------//
`ifdef MF_debug

    //ILA
    /*ila_16x8 ila_MF_inst(
             .clk(clk),
             .probe0(dini),
             .probe1(dinq),
             .probe2(start),
             .probe3(matchfilterout_i),
             .probe4(matchfilterout_q),
             .probe5(MF_rdy),
             .probe6(8'b0),
             .probe7(8'b0)
         );*/



`endif

endmodule