`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: liu yongxin
// 
// Create Date: 08/23/2022 11:58:14 AM
// Design Name: 
// Module Name: ad9361_dp_fdd_1r1t
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: ad9361 degital port config - FDD, 1R1T, Dual Port, DDR
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module ad9361_dp_fdd_1r1t (
    // Receive
    input         rx_clk,
    input  [11:0] rx_data,
    input         rx_frame,
    output [11:0] rx_data_i,
    output [11:0] rx_data_q,
    output        rx_frame_i,
    output        rx_frame_q,
    // Transmit
    input         tx_clk,
    input  [11:0] tx_data_i,
    input  [11:0] tx_data_q,
    output [11:0] tx_data,
    output        tx_frame
);

    // rx data
    genvar i;
    generate
        for (i = 0; i < 12; i = i + 1) begin : rx_data_iddr
            IDDR #(
                .DDR_CLK_EDGE("SAME_EDGE"),
                .INIT_Q1     (1'b0),
                .INIT_Q2     (1'b0),
                .SRTYPE      ("ASYNC")
            ) rx_data_iddr_inst (
                .CE(1'b1),
                .R (1'b0),
                .S (1'b0),
                .C (rx_clk),
                .D (rx_data[i]),
                .Q1(rx_data_q[i]),
                .Q2(rx_data_i[i])
            );
        end
    endgenerate
    // rx frame
    IDDR #(
        .DDR_CLK_EDGE("SAME_EDGE"),
        .INIT_Q1     (1'b0),
        .INIT_Q2     (1'b0),
        .SRTYPE      ("ASYNC")
    ) i_rx_frame_iddr (
        .CE(1'b1),
        .R (1'b0),
        .S (1'b0),
        .C (rx_clk),
        .D (rx_frame),
        .Q1(rx_frame_q),
        .Q2(rx_frame_i)
    );

    // tx data
    generate
        for (i = 0; i < 12; i = i + 1) begin : tx_data_oddr
            ODDR #(
                .DDR_CLK_EDGE("SAME_EDGE"),
                .INIT        (1'b0),
                .SRTYPE      ("ASYNC")
            ) tx_data_oddr_inst (
                .CE(1'b1),
                .R (1'b0),
                .S (1'b0),
                .C (tx_clk),
                .D1(tx_data_i[i]),
                .D2(tx_data_q[i]),
                .Q (tx_data[i])
            );
        end
    endgenerate
    // tx frame
    ODDR #(
        .DDR_CLK_EDGE("SAME_EDGE"),
        .INIT        (1'b0),
        .SRTYPE      ("ASYNC")
    ) i_tx_frame_oddr (
        .CE(1'b1),
        .R (1'b0),
        .S (1'b0),
        .C (tx_clk),
        .D1(1'b0),
        .D2(1'b1),
        .Q (tx_frame)
    );

endmodule