`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/04/26 17:05:11
// Design Name: 
// Module Name: tb_tdma
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_tdma ();



    reg clk = 1;
    reg clk_tx = 1;
    reg rst = 1;
    always #1 clk <= ~clk;
    initial begin
        #1000 rst <= 1'b0;
    end

    wire flag_frame_sync_m;
    reg  flag_frame_sync_s = 0;
    wire intr_2ps_m;
    wire intr_2ps_s;
    wire tic_hop_m;
    wire tic_hop_s;
    wire tx_start_m;
    wire tx_start_s;

    assign flag_frame_sync_m = 1'b0;

    tdma #(
        .SLOT_LEN      (1250000),
        .TIC_TO_PS_LEN (1200000),
        .TIC_FRAME_SYNC(42272)
    ) u_tdma_master (
        .clk            (clk),
        .rst            (rst),
        .flag_is_master (1'b1),
        .flag_frame_sync(flag_frame_sync_m),
        .intr_2ps       (intr_2ps_m),
        // .tic_hop        (tic_hop_m),
        .tx_start       (tx_start_m)
    );


    tdma #(
        .SLOT_LEN      (20000),
        .TIC_TO_PS_LEN (18000),
        .TIC_FRAME_SYNC(2000)
    ) u_tdma_slave (
        .clk            (clk),
        .rst            (rst),
        .flag_is_master (1'b0),
        .flag_frame_sync(flag_frame_sync_s),
        .intr_2ps       (intr_2ps_s),
        // .tic_hop        (tic_hop_s),
        .tx_start       (tx_start_s)
    );


    initial begin
        #12000 flag_frame_sync_s <= 1'b1;
        #3 flag_frame_sync_s <= 1'b0;
    end

endmodule