`timescale 1ns / 1ns
// * Engineer: 
// * *************************************************** *
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// * *************************************************** *
// * Create Date: 2024/04/08
// * Update Date: 2024/05/17

// ! PLEASE MAKE SURE THE PARAMETER ARE VALID 
// ! WHEN U INSTANTIATE THIS MODULE
module tdma #(
    parameter SLOT_LEN = 1250000,
    parameter TIC_TO_PS_LEN = 1200000,
    parameter TIC_FRAME_SYNC = 42272
) (
    input  clk,
    input  rst,
    input  flag_is_master,
    input  flag_frame_sync,
    output intr_2ps,
    // output tic_hop,
    output tx_start
);

    // TODO: 需要检查综合后电路是否会被优化
    // BUG: 需要修复bug，重构代码，把主从分开写，通过参数进行优化
    // ******** Wire & Reg  ********
    reg flag_is_tx_slot;
    // ******** Assingment  ********

    // ******** Logic Block ********

    generate
        if (SLOT_LEN <= 65535) begin  // slot len is small
            reg [15:0] cnt;
            always @(posedge clk) begin
                if (rst) begin
                    cnt <= 16'd0;
                end
                else begin
                    if (!flag_is_master && flag_frame_sync) begin
                        // slave update cnt
                        cnt <= TIC_FRAME_SYNC;
                    end
                    else if (cnt >= SLOT_LEN - 1) begin
                        cnt <= 16'd0;
                    end
                    else begin
                        cnt <= cnt + 16'd1;
                    end
                end
            end
            assign tx_start = flag_is_tx_slot & (cnt == 16'd10);  // just a num for avoiding the zero,(cnt is also 0 in rst state)
            assign intr_2ps = ~flag_is_tx_slot & (cnt == TIC_TO_PS_LEN);

            always @(posedge clk) begin
                if (rst) begin
                    flag_is_tx_slot <= 0;
                end
                else if (!flag_is_master && flag_frame_sync) begin
                    flag_is_tx_slot <= 0;
                end
                else if (cnt == 16'd1) begin
                    flag_is_tx_slot <= ~flag_is_tx_slot;
                end
            end
        end
        else begin
            reg [15:0] cnt_l;
            reg [ 7:0] cnt_h;
            always @(posedge clk) begin
                if (rst) begin
                    cnt_l <= 16'd0;
                    cnt_h <= 8'd0;
                end
                else begin
                    if (!flag_is_master && flag_frame_sync) begin
                        // slave update cnt
                        {cnt_h, cnt_l} <= TIC_FRAME_SYNC;
                    end
                    else begin
                        // master
                        if ({cnt_h, cnt_l} >= SLOT_LEN) begin
                            cnt_h <= 8'd0;
                            cnt_l <= 16'd0;
                        end
                        else begin
                            {cnt_h, cnt_l} <= {cnt_h, cnt_l} + 24'd1;
                        end
                    end
                end
            end
            assign tx_start = flag_is_tx_slot & ({cnt_h, cnt_l} == 16'd10);
            assign intr_2ps = ~flag_is_tx_slot & ({cnt_h, cnt_l} == TIC_TO_PS_LEN);

            always @(posedge clk) begin
                if (rst) begin
                    flag_is_tx_slot <= 0;
                end
                else if (!flag_is_master && flag_frame_sync) begin
                    flag_is_tx_slot <= 0;
                end
                else if ({cnt_h, cnt_l} == 16'd1) begin
                    flag_is_tx_slot <= ~flag_is_tx_slot;
                end
            end
        end
    endgenerate


    // ********    Inst     ********

    // ********    Debug    ********

endmodule