`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 17:42 11/14/2019 // Design Name: // Module Name: RecvTop // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module RecvTop ( input clk, input clk2, input clk_60M_mac, input rst, input rst2, input [11:0] dini, input [11:0] dinq, //视频数据存储，shx input [13:0] recv_addr_new_0, input [13:0] recv_addr_new_1, input [13:0] recv_addr_new_2, input [13:0] recv_addr_new_3, output [ 7:0] recv_data_new_0, output [ 7:0] recv_data_new_1, output [ 7:0] recv_data_new_2, output [ 7:0] recv_data_new_3, output [16:0] RAMaddra_write_0, output [16:0] RAMaddra_write_1, output [16:0] RAMaddra_write_2, output [16:0] RAMaddra_write_3, output [16:0] RAMaddra_new_0, output [16:0] RAMaddra_new_1, output [16:0] RAMaddra_new_2, output [16:0] RAMaddra_new_3, output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕 output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐 //vio // input DC_move_able, //为1的时候启用去直流，为0的时候不启用 // input [1:0] vio_powertest_h, //DAGC // input [1:0] vio_powertest_l, //DAGC // input DAGC_enab, //为1的时候启用DAGC，为0的时候不启用DAGC // input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路 // input EQUenable_vio, //为1时启用均衡 // input [7:0] Zerozone_vio, //零域估计，默认值为8'd29 input [6:0] vio_stopbit, //寻找停止位，默认值为7'd60 //9361、射频增益控制 output [7:0] data_9361, output [9:0] addr_9361, output enab_9361, output D1_12dB, output D2_6dB, output D3_18dB, output D4_12dB, //debug //trigger output rst_TimeSync, output rst_freq, output DAGC_rdy, output framesync, //帧同步峰 output framesync_delay, //帧同步峰，与频率补偿输出对应 output framesync_tsync, //帧同步标志，与TSync输出对应 output IntpARdy, //TSync输出nd output nd_SC_FDE_dout, //SC_FDE输出nd output framerdy, //一帧译码结果存储完毕标志 output reg flag_bercount = 1'd0, output reg flag_badframe = 1'd0, output reg flag_ber = 1'd0, //各模块输出，星座图 output [11:0] dc_removal_dout_i, //MGC_adaptation、去直流输出 output [11:0] dc_removal_dout_q, output [ 9:0] matchfilterout_i, //MF输出 output [ 9:0] matchfilterout_q, output [ 9:0] DAGC_out_i, //DAGC输出 output [ 9:0] DAGC_out_q, output [ 9:0] freqdataout_i, //频率补偿输出 output [ 9:0] freqdataout_q, output [ 9:0] IntpOuti, //TSync输出 output [ 9:0] IntpOutq, output [ 9:0] SC_FDE_douti, //SC_FDE输出 output [ 9:0] SC_FDE_doutq, //MGC_adaptation output [24:0] mean_temp, output [12:0] acc_mean, output [ 4:0] state_mgc, output mgc1_rdy, output flag_state_mgc, output [ 2:0] state_rst, output flag_overflow, output flag_small, //DC output [11:0] dc_value_i, output [11:0] dc_value_q, output flag_dc, //DAGC output flag_agch, output flag_agcl, output flag_agc_power, output [12:0] agc_ref, output [12:0] agc_check, //power test output flag_powerabsh, output flag_powerabsl, output flag_abs_power, output [10:0] abs_ref, output [10:0] abs_check, //TSync output [ 3:0] flag_clk_4bit, //位同步选取通道结果 //SC_FDE,溢出标志 output flagoverflow_fftpilot_26to14, //第1个fft结果截位，即导频fft结果的截位，26截到14 output flagoverflow_ChnZF_26to18, //第2个fft结果截位，即ZF信道估计结果的截位，26截到18 output flagoverflow_comdiv_34to20i, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18 output flagoverflow_comdiv_34to20q, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18 output flagoverflow_ifftzero_29to17i, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17 output flagoverflow_ifftzero_29to17q, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17 output flagoverflow_MMSEdiv_divisor_31to28, //第2个除法器，即MMSE除法的分母截位，31截到28 output flagoverflow_divmmse_34to11, //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11 output flagoverflow_ifftindata_28to20i, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20 output flagoverflow_ifftindata_28to20q, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20 output flagoverflow_fftdata_26to16i, //数据段ow的fft输出截位，26截到16 output flagoverflow_fftdata_26to16q, //数据段ow的fft输出截位，26截到16 output flagoverflow_FDE_dataout_29to10i, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10 output flagoverflow_FDE_dataout_29to10q, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10 output reg flagoverflow = 1'd0, //总溢出标志 output Pilot_rdy_hide1_d1, output [63:0] recvNetData, output recvNetDataNd, input debug_loss // input [ 7:0] MAC_idNum // input [ 7:0] video_id01, // input [ 7:0] video_id02, // input [ 7:0] video_id03 ); MGC_adaptation MGC_adaptation ( .clk (clk), .rst (rst), .dini(dini), .dinq(dinq), .data_9361(data_9361), .addr_9361(addr_9361), .enab_9361(enab_9361), .D1_12dB (D1_12dB), .D2_6dB (D2_6dB), .D3_18dB (D3_18dB), .D4_12dB (D4_12dB), .mgc1_rdy(mgc1_rdy) ); wire MF_rdy; wire MF_rst; MF_Top MF_Top ( .clk(clk), .rst(rst), // .rst (rst), .dini (dini), .dinq (dinq), .start(mgc1_rdy), .matchfilterout_i(matchfilterout_i), .matchfilterout_q(matchfilterout_q), .MF_rdy (MF_rdy), .MF_rst (MF_rst) ); //帧同步模块 assign FrameSync_dini = (DAGC_enab) ? DAGC_out_i : matchfilterout_i; assign FrameSync_dinq = (DAGC_enab) ? DAGC_out_q : matchfilterout_q; // wire framesync; wire Sync_rdy; wire Pilot_rdy; wire [9:0] FrameSync_douti; wire [9:0] FrameSync_doutq; SCFDE_recv_FrameSync SCFDE_recv_FrameSync_inst ( .clk (clk), .rst (MF_rst), .rst_ready (~MF_rdy), .datain_i (matchfilterout_i), .datain_q (matchfilterout_q), .Sync_i (FrameSync_douti), .Sync_q (FrameSync_doutq), .Sync_rdy (Sync_rdy), // 帧同步找到了过门限峰值 .Pilot_rdy (Pilot_rdy),// 开始取导频的标志位 not used .flag_sync (framesync), // high level flag .Pilot_rdy_hide1_d1(Pilot_rdy_hide1_d1) // not used ); // reg [20:0] cnt_lost; reg framelost; always @(posedge clk) begin if (Pilot_rdy_hide1_d1) begin cnt_lost <= 21'd0; framelost <= 1'b0; end else begin if (cnt_lost >= 21'd750000) begin ; cnt_lost <= 21'd0; framelost <= 1'b1; end else begin cnt_lost <= 21'd1 + cnt_lost; framelost <= 1'b0; end end end // wire [9:0] DAGC_out_i; // wire [9:0] DAGC_out_q; // wire flag_agch; // wire flag_agcl; // wire flag_agc_power; // wire [12:0] agc_ref; // wire [12:0] agc_check; wire dagc_rdy; wire mgc_rdy; wire rst_dagc; DAGC_v2 DAGC_v2 ( .clk (clk), .rst (~mgc1_rdy), .mgc1_rdy (MF_rdy), .framesync_d0 (framesync), .vio_powertest_h (2'b00), .vio_powertest_l (2'b00), .matchfilterout_i(FrameSync_douti), .matchfilterout_q(FrameSync_doutq), .DAGC_out_i(DAGC_out_i), .DAGC_out_q(DAGC_out_q), .flag_agch (flag_agch), .flag_agcl (flag_agcl), .flag_agc_power(flag_agc_power), .agc_ref (agc_ref), .agc_check (agc_check), .dagc_rdy (dagc_rdy), .mgc_rdy (mgc_rdy), .rst_dagc (rst_dagc) ); //载波频偏补偿 // wire [9:0] freqdataout_i; // wire [9:0] freqdataout_q; // wire framesync_delay; wire data_save; //debug用，暂不需使用 // wire rst_freq; freqestm freqestm ( .clk (clk), .rst (MF_rst), .mgc_rdy (mgc_rdy), .framesync (dagc_rdy), .datain_i (DAGC_out_i), .datain_q (DAGC_out_q), .dataout_i (freqdataout_i), .dataout_q (freqdataout_q), .framesync_delay(framesync_delay), .data_save (data_save), .rst_freq (rst_freq) ); //位同步 wire [1:0] cnt_tsync; // wire framesync_tsync; //帧同步标志 TimeSync_top TimeSync_top ( .clk (clk), .rst (Pilot_rdy_hide1_d1), .dini (freqdataout_i), .dinq (freqdataout_q), .rdy (IntpARdy), .douti (IntpOuti), .doutq (IntpOutq), .vio_tsync_inter16(vio_tsync_inter16), .framesync (framesync_delay), //帧同步标志 .framesync_tsync (framesync_tsync), //帧同步标志 //debug .cnt_tsync (cnt_tsync), .flag_clk_4bit (flag_clk_4bit) ); // SC-FDE SC_FDE_TOP SC_FDE_TOP_djy ( .clk(clk), .rst(Pilot_rdy_hide1_d1), .EQUenable_vio(EQUenable_vio), //为1时启用均衡 .Zerozone_vio (Zerozone_vio), //零域估计，默认值为8'd29 .flag_ow_left (framesync_tsync), //在一帧内，与第一个数据段的pilot的ow第一个nd对齐 .nd (IntpARdy), .dini (IntpOuti), .dinq (IntpOutq), .nd_SC_FDE_dout (nd_SC_FDE_dout), .SC_FDE_douti (SC_FDE_douti), .SC_FDE_doutq (SC_FDE_doutq), // debug,溢出标志 .flagoverflow_fftpilot_26to14 (flagoverflow_fftpilot_26to14), .flagoverflow_ChnZF_26to18 (flagoverflow_ChnZF_26to18), .flagoverflow_comdiv_34to20i (flagoverflow_comdiv_34to20i), .flagoverflow_comdiv_34to20q (flagoverflow_comdiv_34to20q), .flagoverflow_ifftzero_29to17i (flagoverflow_ifftzero_29to17i), .flagoverflow_ifftzero_29to17q (flagoverflow_ifftzero_29to17q), .flagoverflow_MMSEdiv_divisor_31to28(flagoverflow_MMSEdiv_divisor_31to28), .flagoverflow_divmmse_34to11 (flagoverflow_divmmse_34to11), .flagoverflow_ifftindata_28to20i (flagoverflow_ifftindata_28to20i), .flagoverflow_ifftindata_28to20q (flagoverflow_ifftindata_28to20q), .flagoverflow_fftdata_26to16i (flagoverflow_fftdata_26to16i), .flagoverflow_fftdata_26to16q (flagoverflow_fftdata_26to16q), .flagoverflow_FDE_dataout_29to10i (flagoverflow_FDE_dataout_29to10i), .flagoverflow_FDE_dataout_29to10q (flagoverflow_FDE_dataout_29to10q) ); wire phase_adjust_rdy; wire [9:0] phase_adjust_douti; wire [9:0] phase_adjust_doutq; phase_adjust phase_adjust ( .clk (clk), .rst (Pilot_rdy_hide1_d1), .din_i (SC_FDE_douti), .din_q (SC_FDE_doutq), .nd (nd_SC_FDE_dout), .framesync(framesync_tsync), .rdy (phase_adjust_rdy), .dout_i (phase_adjust_douti), .dout_q (phase_adjust_doutq) ); wire IQmergerdy; wire ldpcsyncin; wire [7:0] IQmergedout; IQmerge IQmerge ( .clk (clk), .clk2 (clk2), .rst (rst2 || Pilot_rdy_hide1_d1), .nd (phase_adjust_rdy), .framesync (framesync_tsync), .dini (phase_adjust_douti), .dinq (phase_adjust_doutq), .rdy (IQmergerdy), .ldpcsyncin(ldpcsyncin), .dout (IQmergedout) ); wire LDPC_SyncOut; wire LDPC_Rdy; wire LDPC_Dout; wire [8:0] good_frames; wire [8:0] bad_frames; wire [8:0] total_frames; CCSDS_LDPC_DEC_K1024_R12_TOPP LDPC_decode ( .clk (clk2), .Rst (rst2 || Pilot_rdy_hide1_d1), .FrameSync (ldpcsyncin), .Nd (IQmergerdy), .Din (IQmergedout), .LDPC_SyncOut(LDPC_SyncOut), .Rdy (LDPC_Rdy), .LDPC_Dout (LDPC_Dout), .good_frames (good_frames), .bad_frames (bad_frames), .total_frames(total_frames) ); wire flag_notbyte; //为1时说明得到的有效数据不以字节为单位 wire [ 1:0] state_ram; wire berstart_1d; wire bercompare; wire [16:0] bercount; wire [16:0] bercount_max; wire [16:0] ROMaddra_d2; wire RAMdout_d1; wire validnd_new_new; wire [63:0] stop_temp_new; wire flag_stop_0; //给shx，拉高1个clk表示当前时帧有效数据接收完毕 wire [16:0] addr_stop_0; wire [ 2:0] cnt_8; wire state_8; wire rdy_scramble; wire dout_scramble; wire [16:0] RAMaddra; //比较误码率 wire [16:0] ROMaddra; //比较误码率 wire nd_ber; FrameMerge FrameMerge ( .clk (clk2), .rst (Pilot_rdy_hide1_d1), .rst2(rst2), .sync(LDPC_SyncOut), .nd (LDPC_Rdy), .din (LDPC_Dout), .vio_stopbit(vio_stopbit), .frameIDnd(Pilot_rdy_hide1_d1), .clk2 (clk_60M_mac), .framerdy (framerdy), .recv_addr_new_0 (recv_addr_new_0), .recv_addr_new_1 (recv_addr_new_1), .recv_addr_new_2 (recv_addr_new_2), .recv_addr_new_3 (recv_addr_new_3), .recv_data_new_0 (recv_data_new_0), .recv_data_new_1 (recv_data_new_1), .recv_data_new_2 (recv_data_new_2), .recv_data_new_3 (recv_data_new_3), .RAMaddra_write_0(RAMaddra_write_0), .RAMaddra_write_1(RAMaddra_write_1), .RAMaddra_write_2(RAMaddra_write_2), .RAMaddra_write_3(RAMaddra_write_3), .RAMaddra_new_0 (RAMaddra_new_0), .RAMaddra_new_1 (RAMaddra_new_1), .RAMaddra_new_2 (RAMaddra_new_2), .RAMaddra_new_3 (RAMaddra_new_3), .flag_notbyte(flag_notbyte), .state_ram (state_ram), .flag_stop (flag_stop), //给shx，拉高8个clk表示当前时帧有效数据接收完毕 .addr_stop (addr_stop), //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐 //debug .berstart_1d (berstart_1d), .bercompare (bercompare), .bercount (bercount), .bercount_max(bercount_max), .ROMaddra_d2 (ROMaddra_d2), .RAMdout_d1 (RAMdout_d1), .validnd_new_new(validnd_new_new), .stop_temp_new(stop_temp_new), .flag_stop_0(flag_stop_0), .addr_stop_0(addr_stop_0), .cnt_8 (cnt_8), .state_8 (state_8), .rdy_scramble (rdy_scramble), .dout_scramble(dout_scramble), .RAMaddra (RAMaddra), .ROMaddra (ROMaddra), .nd_ber (nd_ber), .recvNetData (recvNetData), .recvNetDataNd(recvNetDataNd) // .MAC_idNum (MAC_idNum) // .video_id01 (8'd0), // .video_id02 (8'd0), // .video_id03 (8'd0) ); /*ila_recvtop ila_recvtop( .clk(clk), .probe0(framesync), .probe1(framesync_delay), .probe2(phase_adjust_rdy), .probe3(nd_SC_FDE_dout), .probe4(IQmergerdy), .probe5(IQmergedout), .probe6(LDPC_Rdy), .probe7(LDPC_Dout), .probe8(SC_FDE_douti), .probe9(SC_FDE_doutq), .probe10(total_frames), .probe11(good_frames), .probe12(dini), .probe13(dinq), .probe14(phase_adjust_douti), .probe15(phase_adjust_doutq), .probe16(D1_12dB), .probe17(D2_6dB), .probe18(D3_18dB), .probe19(D4_12dB) );*/ ila_recvtest ila_recvtest ( .clk (clk), .probe0(framesync), .probe1(framesync_delay), .probe2(D1_12dB), .probe3(D2_6dB), .probe4(D3_18dB), .probe5(D4_12dB), .probe6(mgc1_rdy), .probe7(rst), .probe8(dini), .probe9(dinq) ); /*ila_decode ila_decode( .clk(clk2), .probe0(IQmergerdy), .probe1(IQmergedout), .probe2(LDPC_Dout), .probe3(LDPC_Rdy), .probe4(framerdy), .probe5(total_frames), .probe6(good_frames) );*/ endmodule