#ifndef __PHY_CONTROL_H__
#define __PHY_CONTROL_H__

#include "xil_io.h"
#include "xparameters.h"
#include "mac.h"

#define PHY_CONTROL_BASEADDR XPAR_PHY_CONTROL_0_BASEADDR

#define PHY_REG_CONTROL_ADDR 0x00000000
#define CONTROL_REG_PHY_RST_OFFSET 0x0
#define PHY_RST_MASK 0xFFFE
#define PHY_RST_ON  0x0 // active low
#define PHY_RST_OFF 0x1


#define CONTROL_REG_TX_TEST_FLAG_OFFSET 0x1
#define PHY_TX_TEST_FLAG_MASK 0xFFFD
#define PHY_TX_TEST_ON 0x1
#define PHY_TX_TEST_OFF 0x0

#define CONTROL_REG_TX_IQ_REVERSE_FLAG_OFFSET 0x2
#define CONTROL_REG_RX_IQ_REVERSE_FLAG_OFFSET 0x3

#define PHY_REG_STATUS_ADDR 0x00000004
#define PHY_REG_TDMA_SLOT_LEN_ADDR 0x00000008
#define PHY_REG_TDMA_TIC_2_PS_ADDR 0x0000000C
#define PHY_REG_TDMA_ID_CFG_ADDR 0x00000010
#define PHY_REG_TDMA_RECV_ID_ADDR 0x00000014
#define PHY_REG_TDMA_FRAME_SYNC_TIC_ADDR 0x00000018


#define W32(reg_addr, val) Xil_Out32(PHY_CONTROL_BASEADDR + (reg_addr),(val))
#define R32(reg_addr) Xil_In32(PHY_CONTROL_BASEADDR + (reg_addr))


// parameters
#define PHY_TX_REVERSE 0
#define PHY_RX_REVERSE 1
#define TDMA_LOCAL_ID 2
#define TDMA_SLOT_NUM 2

//#define SPEED_INTERP_4
#define SPEED_INTERP_16

#if defined(SPEED_INTERP_4)
#define SLOT_LEN 750000
#define TIC_2_PS 600000
#define FRAME_SYNC_TIC 44670
//#define SLOT_LEN 625001
//#define TIC_2_PS 500000
#elif defined(SPEED_INTERP_16)
//#define SLOT_LEN 2750000
//#define TIC_2_PS 2000000
#define FRAME_SYNC_TIC 178250
#define SLOT_LEN 2500004
#define TIC_2_PS 2000000

#else //default interp 4 mode
#define SLOT_LEN 750000
#define TIC_2_PS 600000
#endif

extern uint8_t tdmaId;
extern uint8_t tdmaSlotNum;

// function declaration
void  PhyRstOn();

void  PhyRstOff();


void  PhyTxTestOn();

void  PhyTxTestOff();

// configure tdma parameters
void PhyConfigTdma(uint8_t localId,uint8_t slotNum,uint32_t slotLen,uint32_t ticTime);


void PhyInit();

int PhyUpdateCurSlot(uint8_t recvId);

#endif
