#include "phy_control.h"
#include "log.h"

uint8_t tdmaId;
uint8_t tdmaSlotNum;

void  PhyRstOn()
{
	u32 v = R32(PHY_REG_CONTROL_ADDR) & PHY_RST_MASK ;
	W32(PHY_REG_CONTROL_ADDR,v);
}

void  PhyRstOff()
{
	u32 v = (R32(PHY_REG_CONTROL_ADDR) & PHY_RST_MASK) | PHY_RST_OFF;
	W32(PHY_REG_CONTROL_ADDR,v);
}


void  PhyTxTestOn()
{
	PhyRstOn();
	u32 v = (R32(PHY_REG_CONTROL_ADDR) & PHY_TX_TEST_FLAG_MASK) | (PHY_TX_TEST_ON << CONTROL_REG_TX_TEST_FLAG_OFFSET);
	W32(PHY_REG_CONTROL_ADDR,v);
	PhyRstOff();
}


void  PhyTxTestOff()
{
	PhyRstOn();
	u32 v = (R32(PHY_REG_CONTROL_ADDR) & PHY_TX_TEST_FLAG_MASK) | (PHY_TX_TEST_OFF << CONTROL_REG_TX_TEST_FLAG_OFFSET);
	W32(PHY_REG_CONTROL_ADDR,v);
	PhyRstOff();
}

void PhyConfigTdma(uint8_t localId,uint8_t slotNum,uint32_t slotLen,uint32_t ticTime)
{
	W32(PHY_REG_TDMA_SLOT_LEN_ADDR,slotLen);
	W32(PHY_REG_TDMA_TIC_2_PS_ADDR,ticTime);
	W32(PHY_REG_TDMA_ID_CFG_ADDR,((uint32_t)slotNum << 8 | (uint32_t)localId));
	W32(PHY_REG_TDMA_FRAME_SYNC_TIC_ADDR ,FRAME_SYNC_TIC);
}

void PhyInit()
{
	uint32_t control=0;
	// set phy reset on
	control = (PHY_RST_ON<<CONTROL_REG_PHY_RST_OFFSET) | \
			(PHY_TX_TEST_OFF << CONTROL_REG_TX_TEST_FLAG_OFFSET) | \
			(PHY_TX_REVERSE << CONTROL_REG_TX_IQ_REVERSE_FLAG_OFFSET) | \
			(PHY_RX_REVERSE << CONTROL_REG_RX_IQ_REVERSE_FLAG_OFFSET)
			;
	W32(PHY_REG_CONTROL_ADDR,control);
	PhyConfigTdma(tdmaId,tdmaSlotNum,SLOT_LEN,TIC_2_PS);
	xil_printf(INFO_MSG("TDMA ID: %d\tSlot Number: %d"),tdmaId,tdmaSlotNum);
#if defined(SPEED_INTERP_4)
	LOG_INFO("SPEED_INTERP_4");
#elif defined(SPEED_INTERP_16)
	LOG_INFO("SPEED_INTERP_16");
#endif

	xil_printf(INFO_MSG("SLOT LEN: %d ms"),SLOT_LEN/50000);


}

int PhyUpdateCurSlot(uint8_t recvId)
{
	if( recvId!=tdmaId && recvId <= tdmaSlotNum && recvId!=0)
	{
		W32( PHY_REG_TDMA_RECV_ID_ADDR , (uint32_t)( 0x01 << 8 | (uint32_t)recvId ));
		return 0;
	}
	return -1;
}
