146 lines
4.3 KiB
Verilog
146 lines
4.3 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/11/18 23:18:07
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// Design Name:
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// Module Name: CCSDS_LDPC_DEC_K1024_R12
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module CCSDS_LDPC_DEC_K1024_R12 #(
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parameter WIDTH = 4'd8,
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parameter MAX_ITER_NUM = 6'd14,
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parameter OUT_ONLY_INFORMATION = 1'b0 //译码输出格式选择标志，1:只输出信息位；0：输出整个码字
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) (
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input clk, //工作时钟,100MHz
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input Rst, //同步复位信号,高有效
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input FrameSync, //帧同步标志,高脉冲
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input Nd, //译码输入数据有效标志,高有效
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input [WIDTH-1:0] Din, //译码输入数据,软信息,数据速率约为12.5Mbps
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output reg LDPC_SyncOut = 1'b0, //LDPC模块帧同步输出信号,高脉冲,指示帧起点
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output reg Rdy = 1'b0, //译码输出信号有效标志,高有效
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output reg [0:0] LDPC_Dout = 1'b0, //译码输出信号
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output reg [8:0] good_frames = 9'd0, //译码好帧计数
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output reg [8:0] bad_frames = 9'd0, //译码坏帧计数
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output reg [8:0] total_frames = 9'd0 //译码总帧计数
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);
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reg rst_MS = 1'd0;
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reg framesync_MS = 1'd0;
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reg nd_MS = 1'd0;
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reg [WIDTH-1:0] din_MS = 8'd0;
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reg oe_MS = 1'd0;
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wire deal_end_MS;
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wire [WIDTH-1:0] dout01_MS;
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wire [WIDTH-1:0] dout02_MS;
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wire [WIDTH-1:0] dout03_MS;
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wire [WIDTH-1:0] dout04_MS;
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always @(posedge clk) begin
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rst_MS <= Rst;
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framesync_MS <= FrameSync;
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nd_MS <= Nd;
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din_MS <= Din;
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end
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//******输入数据的缓存模块
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Message_Store #(
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.WIDTH(WIDTH)
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) MS (
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.clk (clk),
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.rst_MS (rst_MS),
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.framesync_MS(framesync_MS),
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.nd_MS (nd_MS),
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.din_MS (din_MS),
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.oe_MS (oe_MS),
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.deal_end_MS (deal_end_MS),
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.syncout_MS (syncout_MS),
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.rdy_MS (rdy_MS),
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.dout01_MS (dout01_MS),
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.dout02_MS (dout02_MS),
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.dout03_MS (dout03_MS),
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.dout04_MS (dout04_MS)
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);
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reg rst = 1'd0;
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reg start = 1'd0;
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reg framesync = 1'd0;
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reg nd = 1'd0;
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reg [WIDTH-1:0] din01 = 8'd0;
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reg [WIDTH-1:0] din02 = 8'd0;
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reg [WIDTH-1:0] din03 = 8'd0;
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reg [WIDTH-1:0] din04 = 8'd0;
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wire ask_din;
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wire [ 8:0] gd_frames;
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wire [ 8:0] bd_frames;
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wire [ 8:0] tl_frames;
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wire ldpc_syncout;
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wire rdy;
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wire [ 0:0] ldpc_dout;
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always @(posedge clk) begin
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rst <= Rst;
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start <= deal_end_MS;
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framesync <= syncout_MS;
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nd <= rdy_MS;
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din01 <= dout01_MS;
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din02 <= dout02_MS;
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din03 <= dout03_MS;
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din04 <= dout04_MS;
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oe_MS <= ask_din;
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end
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// TOP层译码器输出
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always @(posedge clk) begin
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LDPC_SyncOut <= ldpc_syncout;
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Rdy <= rdy;
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LDPC_Dout <= ldpc_dout;
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good_frames <= gd_frames;
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bad_frames <= bd_frames;
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total_frames <= tl_frames;
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end
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LDPC_DEC_PRO //译码器的吞吐量=(信息比特数/(一次迭代所需的时钟数*迭代次数))*FPGA工作主频
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#(
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.MAX_ITER_NUM(MAX_ITER_NUM),
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.WIDTH(WIDTH),
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.OUT_ONLY_INFORMATION(OUT_ONLY_INFORMATION)
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) LDPC_DEC (
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.clk (clk),
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.rst (rst),
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.start (start),
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.framesync (framesync),
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.nd (nd),
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.din01 (din01),
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.din02 (din02),
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.din03 (din03),
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.din04 (din04),
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.ask_din (ask_din),
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.gd_frames (gd_frames),
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.bd_frames (bd_frames),
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.tl_frames (tl_frames),
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.ldpc_syncout(ldpc_syncout),
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.rdy (rdy),
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.ldpc_dout (ldpc_dout)
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);
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endmodule
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