387 lines
19 KiB
Verilog
387 lines
19 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/11/18 23:18:07
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// Design Name:
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// Module Name: CK_PRO
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module CK_PRO
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#(
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parameter Index_p1_row_01_dec_01_01=0, Index_p1_row_01_dec_02_01=0,
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parameter Index_p1_row_02_dec_02_01=0, Index_p1_row_02_dec_03_01=0,
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parameter Index_p1_row_03_dec_03_01=0, Index_p1_row_03_dec_04_01=0,
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parameter Index_p1_row_04_dec_04_01=0, Index_p1_row_04_dec_01_01=112,
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parameter Index_p2_row_01_dec_05_01=0, Index_p2_row_01_dec_05_02=25, Index_p2_row_01_dec_08_01=31,Index_p2_row_01_dec_07_01=39,
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parameter Index_p2_row_02_dec_06_01=0, Index_p2_row_02_dec_06_02=75, Index_p2_row_02_dec_05_01=23,Index_p2_row_02_dec_08_01=16,
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parameter Index_p2_row_03_dec_07_01=0, Index_p2_row_03_dec_07_02=120,Index_p2_row_03_dec_06_01=54,Index_p2_row_03_dec_05_01=0,
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parameter Index_p2_row_04_dec_08_01=0, Index_p2_row_04_dec_08_02=93, Index_p2_row_04_dec_07_01=9, Index_p2_row_04_dec_06_01=83,
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parameter Index_p3_row_01_dec_09_01=0, Index_p3_row_01_dec_09_02=13, Index_p3_row_01_dec_11_01=97, Index_p3_row_01_dec_10_01=0, Index_p3_row_01_dec_12_01=34,
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parameter Index_p3_row_02_dec_10_01=0, Index_p3_row_02_dec_10_02=69, Index_p3_row_02_dec_12_01=64, Index_p3_row_02_dec_11_01=6, Index_p3_row_02_dec_09_01=98,
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parameter Index_p3_row_03_dec_11_01=0, Index_p3_row_03_dec_11_02=127,Index_p3_row_03_dec_09_01=78, Index_p3_row_03_dec_12_01=35, Index_p3_row_03_dec_10_01=26,
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parameter Index_p3_row_04_dec_12_01=0, Index_p3_row_04_dec_12_02=29, Index_p3_row_04_dec_10_01=81, Index_p3_row_04_dec_09_01=99, Index_p3_row_04_dec_11_01=59
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)
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(
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input clk,
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input rst_OUTCK,
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input start_OUTCK,
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input nd_OUTCK,
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input [0:0] DR_din_01,
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input [0:0] DR_din_02,
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input [0:0] DR_din_03,
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input [0:0] DR_din_04,
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input [0:0] DR_din_05,
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output reg [8:0] gd_frames=9'd0,//译码好帧计数
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output reg [8:0] bd_frames=9'd0,//译码坏帧计数
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output reg [8:0] tl_frames=9'd0 //译码总帧数计数
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);
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reg [127:0] dec_01 = 128'd0, dec_02 = 128'd0, dec_03 = 128'd0, dec_04 = 128'd0;
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reg [127:0] dec_05 = 128'd0, dec_06 = 128'd0, dec_07 = 128'd0, dec_08 = 128'd0;
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reg [127:0] dec_09 = 128'd0, dec_10 = 128'd0, dec_11 = 128'd0, dec_12 = 128'd0;
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reg [127:0] dec_01_d1 = 128'd0, dec_02_d1 = 128'd0, dec_03_d1 = 128'd0, dec_04_d1 = 128'd0;
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reg [127:0] dec_05_d1 = 128'd0, dec_06_d1 = 128'd0, dec_07_d1 = 128'd0, dec_08_d1 = 128'd0;
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reg [127:0] dec_09_d1 = 128'd0, dec_10_d1 = 128'd0, dec_11_d1 = 128'd0, dec_12_d1 = 128'd0;
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reg [10:0] cnt_CK=11'd0;
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reg deal_end=1'd0,deal_end_d1=1'd0,deal_end_d2=1'd0,deal_end_d3=1'd0,deal_end_d4=1'd0,deal_end_d5=1'd0,dec_proc=1'd0;
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// 产生本模块的计数器
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always @ (posedge clk) begin
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if (rst_OUTCK) begin
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dec_proc <= 1'd0;
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cnt_CK <= 11'd0;
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end else begin
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if (start_OUTCK) begin
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dec_proc <= 1'd1;
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cnt_CK <= 11'd0;
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end else begin
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if (dec_proc) begin
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if (cnt_CK < 11'd560) begin
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cnt_CK <= cnt_CK + 11'd1;
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dec_proc <= dec_proc;
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end else begin
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cnt_CK <= cnt_CK;
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dec_proc <= 1'd0;
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end
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end else begin
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cnt_CK <= cnt_CK;
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end
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end
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end
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end
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parameter DELAY_DIN = 11'd0;
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always @ (posedge clk) begin
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if (rst_OUTCK || start_OUTCK) begin
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dec_01 <= 128'd0; dec_01_d1 <= 128'd0;
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dec_02 <= 128'd0; dec_02_d1 <= 128'd0;
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dec_03 <= 128'd0; dec_03_d1 <= 128'd0;
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dec_04 <= 128'd0; dec_04_d1 <= 128'd0;
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dec_05 <= 128'd0; dec_05_d1 <= 128'd0;
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dec_06 <= 128'd0; dec_06_d1 <= 128'd0;
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dec_07 <= 128'd0; dec_07_d1 <= 128'd0;
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dec_08 <= 128'd0; dec_08_d1 <= 128'd0;
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dec_09 <= 128'd0; dec_09_d1 <= 128'd0;
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dec_10 <= 128'd0; dec_10_d1 <= 128'd0;
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dec_11 <= 128'd0; dec_11_d1 <= 128'd0;
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dec_12 <= 128'd0; dec_12_d1 <= 128'd0;
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deal_end <= 1'd0;
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end else begin
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// 本来3行5列的H矩阵转置后变成5行3列
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// 第1列（4*128=512）个校验子求解过程
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if (cnt_CK >= 11'd1 + DELAY_DIN && cnt_CK < 11'd129 + DELAY_DIN) begin
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dec_01[Index_p1_row_01_dec_01_01] <= DR_din_03 ^ DR_din_05;
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dec_02[Index_p1_row_01_dec_02_01] <= DR_din_05;
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end else if (cnt_CK >= 11'd129 + DELAY_DIN && cnt_CK < 11'd257 + DELAY_DIN) begin
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dec_01[Index_p1_row_01_dec_01_01] <= 1'd0;
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dec_02[Index_p1_row_02_dec_02_01] <= DR_din_03 ^ DR_din_05;
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dec_03[Index_p1_row_02_dec_03_01] <= DR_din_05;
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end else if (cnt_CK >= 11'd257 + DELAY_DIN && cnt_CK < 11'd385 + DELAY_DIN) begin
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dec_03[Index_p1_row_03_dec_03_01] <= DR_din_03 ^ DR_din_05;
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dec_04[Index_p1_row_03_dec_04_01] <= DR_din_05;
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end else if (cnt_CK >= 11'd385 + DELAY_DIN && cnt_CK < 11'd513 + DELAY_DIN) begin
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dec_04[Index_p1_row_04_dec_04_01] <= DR_din_03 ^ DR_din_05;
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dec_01[Index_p1_row_04_dec_01_01] <= DR_din_05;
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end else begin
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dec_01 <= dec_01;
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dec_02 <= dec_02;
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dec_03 <= dec_03;
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dec_04 <= dec_04;
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end
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if (cnt_CK >= 11'd2 + DELAY_DIN && cnt_CK < 11'd130 + DELAY_DIN) begin
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dec_01_d1 <= {dec_01_d1[0],dec_01_d1[127:1]} ^ dec_01;
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dec_02_d1 <= {dec_02_d1[0],dec_02_d1[127:1]} ^ dec_02;
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end else if (cnt_CK >= 11'd130 + DELAY_DIN && cnt_CK < 11'd258 + DELAY_DIN) begin
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dec_02_d1 <= {dec_02_d1[0],dec_02_d1[127:1]} ^ dec_02;
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dec_03_d1 <= {dec_03_d1[0],dec_03_d1[127:1]} ^ dec_03;
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end else if (cnt_CK >= 11'd258 + DELAY_DIN && cnt_CK < 11'd386 + DELAY_DIN) begin
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dec_03_d1 <= {dec_03_d1[0],dec_03_d1[127:1]} ^ dec_03;
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dec_04_d1 <= {dec_04_d1[0],dec_04_d1[127:1]} ^ dec_04;
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end else if (cnt_CK >= 11'd386 + DELAY_DIN && cnt_CK < 11'd514 + DELAY_DIN) begin
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dec_04_d1 <= {dec_04_d1[0],dec_04_d1[127:1]} ^ dec_04;
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dec_01_d1 <= {dec_01_d1[0],dec_01_d1[127:1]} ^ dec_01;
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end else if (cnt_CK == 11'd514 + DELAY_DIN) begin
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dec_01_d1 <= {dec_01_d1[0],dec_01_d1[127:1]};
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dec_02_d1 <= {dec_02_d1[0],dec_02_d1[127:1]};
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dec_03_d1 <= {dec_03_d1[0],dec_03_d1[127:1]};
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dec_04_d1 <= {dec_04_d1[0],dec_04_d1[127:1]};
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end else begin
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dec_01_d1 <= dec_01_d1;
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dec_02_d1 <= dec_02_d1;
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dec_03_d1 <= dec_03_d1;
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dec_04_d1 <= dec_04_d1;
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deal_end <= 1'd0;
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end
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// 第2列（4*128=512）个校验子求解过程
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if (cnt_CK >= 11'd1 + DELAY_DIN && cnt_CK < 11'd129 + DELAY_DIN) begin
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dec_05[Index_p2_row_01_dec_05_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04;
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dec_05[Index_p2_row_01_dec_05_02] <= DR_din_05;
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dec_08[Index_p2_row_01_dec_08_01] <= DR_din_05;
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dec_07[Index_p2_row_01_dec_07_01] <= DR_din_05;
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end else if (cnt_CK >= 11'd129 + DELAY_DIN && cnt_CK < 11'd257 + DELAY_DIN) begin
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dec_06[Index_p2_row_02_dec_06_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04;
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dec_06[Index_p2_row_02_dec_06_02] <= DR_din_05;
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dec_05[Index_p2_row_02_dec_05_01] <= DR_din_05;
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dec_05[Index_p2_row_01_dec_05_01] <= 1'd0;
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dec_05[Index_p2_row_01_dec_05_02] <= 1'd0;
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dec_08[Index_p2_row_02_dec_08_01] <= DR_din_05;
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dec_08[Index_p2_row_01_dec_08_01] <= 1'd0;
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dec_07[Index_p2_row_01_dec_07_01] <= 1'd0; //xhx
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end else if (cnt_CK >= 11'd257 + DELAY_DIN && cnt_CK < 11'd385 + DELAY_DIN) begin
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dec_07[Index_p2_row_03_dec_07_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04;
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dec_07[Index_p2_row_03_dec_07_02] <= DR_din_05;
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dec_06[Index_p2_row_03_dec_06_01] <= DR_din_05;
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dec_06[Index_p2_row_02_dec_06_01] <= 1'd0;
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dec_06[Index_p2_row_02_dec_06_02] <= 1'd0;
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dec_05[Index_p2_row_03_dec_05_01] <= DR_din_05;
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dec_05[Index_p2_row_02_dec_05_01] <= 1'd0;
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dec_08[Index_p2_row_02_dec_08_01] <= 1'd0; //xhx
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end else if (cnt_CK >= 11'd385 + DELAY_DIN && cnt_CK < 11'd513 + DELAY_DIN) begin
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dec_08[Index_p2_row_04_dec_08_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04;
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dec_08[Index_p2_row_04_dec_08_02] <= DR_din_05;
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dec_07[Index_p2_row_04_dec_07_01] <= DR_din_05;
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dec_07[Index_p2_row_03_dec_07_01] <= 1'd0;
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dec_07[Index_p2_row_03_dec_07_02] <= 1'd0;
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dec_06[Index_p2_row_04_dec_06_01] <= DR_din_05;
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dec_06[Index_p2_row_03_dec_06_01] <= 1'd0;
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dec_05[Index_p2_row_03_dec_05_01] <= 1'd0; //xhx
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end else begin
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dec_05 <= dec_05;
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dec_06 <= dec_06;
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dec_07 <= dec_07;
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dec_08 <= dec_08;
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end
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if (cnt_CK >= 11'd2 + DELAY_DIN && cnt_CK < 11'd130 + DELAY_DIN) begin
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dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]} ^ dec_05;
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dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]} ^ dec_07;
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dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]} ^ dec_08;
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end else if (cnt_CK >= 11'd130 + DELAY_DIN && cnt_CK < 11'd258 + DELAY_DIN) begin
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dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]} ^ dec_05;
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dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]} ^ dec_06;
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dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]} ^ dec_08;
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end else if (cnt_CK >= 11'd258 + DELAY_DIN && cnt_CK < 11'd386 + DELAY_DIN) begin
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dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]} ^ dec_05;
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dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]} ^ dec_06;
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dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]} ^ dec_07;
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end else if (cnt_CK >= 11'd386 + DELAY_DIN && cnt_CK < 11'd514 + DELAY_DIN) begin
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dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]} ^ dec_06;
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dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]} ^ dec_07;
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dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]} ^ dec_08;
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end else if (cnt_CK == 11'd514 + DELAY_DIN) begin
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dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]};
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dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]};
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dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]};
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dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]};
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end else begin
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dec_05_d1 <= dec_05_d1;
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dec_06_d1 <= dec_06_d1;
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dec_07_d1 <= dec_07_d1;
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dec_08_d1 <= dec_08_d1;
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end
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// 第3列（4*128=512）个校验子求解过程
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if (cnt_CK >= 11'd1 + DELAY_DIN && cnt_CK < 11'd129 + DELAY_DIN) begin
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dec_09[Index_p3_row_01_dec_09_01] <= DR_din_01 ^ DR_din_05;
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dec_09[Index_p3_row_01_dec_09_02] <= DR_din_04;
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dec_11[Index_p3_row_01_dec_11_01] <= DR_din_02;
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dec_10[Index_p3_row_01_dec_10_01] <= DR_din_02;
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dec_12[Index_p3_row_01_dec_12_01] <= DR_din_04;
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end else if (cnt_CK >= 11'd129 + DELAY_DIN && cnt_CK < 11'd257 + DELAY_DIN) begin
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dec_10[Index_p3_row_02_dec_10_01] <= DR_din_01 ^ DR_din_05;
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dec_10[Index_p3_row_02_dec_10_02] <= DR_din_04;
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dec_12[Index_p3_row_02_dec_12_01] <= DR_din_02;
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dec_12[Index_p3_row_01_dec_12_01] <= 1'd0;
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dec_11[Index_p3_row_02_dec_11_01] <= DR_din_02;
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dec_11[Index_p3_row_01_dec_11_01] <= 1'd0;
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dec_09[Index_p3_row_02_dec_09_01] <= DR_din_04;
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dec_09[Index_p3_row_01_dec_09_01] <= 1'd0;
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dec_09[Index_p3_row_01_dec_09_02] <= 1'd0;
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end else if (cnt_CK >= 11'd257 + DELAY_DIN && cnt_CK < 11'd385 + DELAY_DIN) begin
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dec_11[Index_p3_row_03_dec_11_01] <= DR_din_01 ^ DR_din_05;
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dec_11[Index_p3_row_03_dec_11_02] <= DR_din_04;
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dec_11[Index_p3_row_02_dec_11_01] <= 1'd0;
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dec_09[Index_p3_row_03_dec_09_01] <= DR_din_02;
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dec_09[Index_p3_row_02_dec_09_01] <= 1'd0;
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dec_12[Index_p3_row_03_dec_12_01] <= DR_din_02;
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dec_12[Index_p3_row_02_dec_12_01] <= 1'd0;
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dec_10[Index_p3_row_03_dec_10_01] <= DR_din_04;
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dec_10[Index_p3_row_02_dec_10_01] <= 1'd0;
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dec_10[Index_p3_row_02_dec_10_02] <= 1'd0;
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end else if (cnt_CK >= 11'd385 + DELAY_DIN && cnt_CK < 11'd513 + DELAY_DIN) begin
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dec_12[Index_p3_row_04_dec_12_01] <= DR_din_01 ^ DR_din_05;
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dec_12[Index_p3_row_04_dec_12_02] <= DR_din_04;
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dec_12[Index_p3_row_03_dec_12_01] <= 1'd0;
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dec_10[Index_p3_row_04_dec_10_01] <= DR_din_02;
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dec_10[Index_p3_row_03_dec_10_01] <= 1'd0;
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dec_09[Index_p3_row_04_dec_09_01] <= DR_din_02;
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dec_09[Index_p3_row_03_dec_09_01] <= 1'd0;
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dec_11[Index_p3_row_04_dec_11_01] <= DR_din_04;
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dec_11[Index_p3_row_03_dec_11_01] <= 1'd0;
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dec_11[Index_p3_row_03_dec_11_02] <= 1'd0;
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end else begin
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dec_09 <= dec_09;
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dec_10 <= dec_10;
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dec_11 <= dec_11;
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dec_12 <= dec_12;
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end
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if (cnt_CK >= 11'd2 + DELAY_DIN && cnt_CK < 11'd130 + DELAY_DIN) begin
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dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09;
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dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10;
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dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11;
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dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12;
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end else if (cnt_CK >= 11'd130 + DELAY_DIN && cnt_CK < 11'd258 + DELAY_DIN) begin
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dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09;
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dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10;
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dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11;
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dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12;
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end else if (cnt_CK >= 11'd258 + DELAY_DIN && cnt_CK < 11'd386 + DELAY_DIN) begin
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dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09;
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dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10;
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dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11;
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dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12;
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end else if (cnt_CK >= 11'd386 + DELAY_DIN && cnt_CK < 11'd514 + DELAY_DIN) begin
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dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09;
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dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10;
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dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11;
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dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12;
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end else if (cnt_CK == 11'd514 + DELAY_DIN) begin
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dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]};
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dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]};
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dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]};
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dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]};
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end else begin
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dec_09_d1 <= dec_09_d1;
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dec_10_d1 <= dec_10_d1;
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dec_11_d1 <= dec_11_d1;
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dec_12_d1 <= dec_12_d1;
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end
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// 产生标志位
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if (cnt_CK == 11'd514 + DELAY_DIN)
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deal_end <= 1'd1;
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else
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deal_end <= 1'd0;
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end
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end
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//2019.02.28添加：打一拍，尝试避免时序问题
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reg deal_end_d6 = 1'd0;
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reg flag_judge1 = 1'd0;
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reg flag_judge2 = 1'd0;
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reg flag_judge3 = 1'd0;
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always@(posedge clk) begin
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if(rst_OUTCK) begin
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flag_judge1 <= 1'd0;
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flag_judge2 <= 1'd0;
|
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flag_judge3 <= 1'd0;
|
|
end
|
|
else begin
|
|
if(deal_end_d5) begin
|
|
if(dec_01_d1 == 128'd0 && dec_02_d1 == 128'd0 && dec_03_d1 == 128'd0 && dec_04_d1 == 128'd0 ) flag_judge1 <= 1'd0;
|
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else flag_judge1 <= 1'd1;
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if(dec_05_d1 == 128'd0 && dec_06_d1 == 128'd0 && dec_07_d1 == 128'd0 && dec_08_d1 == 128'd0 ) flag_judge2 <= 1'd0;
|
|
else flag_judge2 <= 1'd1;
|
|
if(dec_09_d1 == 128'd0 && dec_10_d1 == 128'd0 && dec_11_d1 == 128'd0 && dec_12_d1 == 128'd0 ) flag_judge3 <= 1'd0;
|
|
else flag_judge3 <= 1'd1;
|
|
end
|
|
else begin
|
|
flag_judge1 <= flag_judge1;
|
|
flag_judge2 <= flag_judge2;
|
|
flag_judge3 <= flag_judge3;
|
|
end
|
|
end
|
|
end
|
|
|
|
|
|
always@(posedge clk) begin
|
|
if(rst_OUTCK) begin
|
|
gd_frames <= 9'd0;
|
|
bd_frames <= 9'd0;
|
|
tl_frames <= 9'd0;
|
|
deal_end_d1 <= 1'd0;
|
|
deal_end_d2 <= 1'd0;
|
|
deal_end_d3 <= 1'd0;
|
|
deal_end_d4 <= 1'd0;
|
|
deal_end_d5 <= 1'd0;
|
|
deal_end_d6 <= 1'd0; //2019.02.28添加
|
|
end else begin
|
|
deal_end_d1 <= deal_end;
|
|
deal_end_d2 <= deal_end_d1;
|
|
deal_end_d3 <= deal_end_d2;
|
|
deal_end_d4 <= deal_end_d3;
|
|
deal_end_d5 <= deal_end_d4;
|
|
deal_end_d6 <= deal_end_d5; //2019.02.28添加
|
|
if(deal_end_d6) begin
|
|
if(flag_judge1 == 1'd0 && flag_judge2 == 1'd0 && flag_judge3 == 1'd0 ) begin
|
|
// if(dec_01_d1 == 128'd0 && dec_02_d1 == 128'd0 && dec_03_d1 == 128'd0 && dec_04_d1 == 128'd0 &&
|
|
// dec_05_d1 == 128'd0 && dec_06_d1 == 128'd0 && dec_07_d1 == 128'd0 && dec_08_d1 == 128'd0 &&
|
|
// dec_09_d1 == 128'd0 && dec_10_d1 == 128'd0 && dec_11_d1 == 128'd0 && dec_12_d1 == 128'd0 ) begin
|
|
gd_frames <= gd_frames + 9'd1;
|
|
bd_frames <= bd_frames;
|
|
tl_frames <= tl_frames + 9'd1;
|
|
end else begin
|
|
gd_frames <= gd_frames;
|
|
bd_frames <= bd_frames + 9'd1;
|
|
tl_frames <= tl_frames + 9'd1;
|
|
end
|
|
end else begin
|
|
gd_frames <= gd_frames;
|
|
bd_frames <= bd_frames;
|
|
tl_frames <= tl_frames;
|
|
end
|
|
end
|
|
end
|
|
|
|
|
|
endmodule
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