212 lines
5.6 KiB
Verilog
212 lines
5.6 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/08/03 14:12:18
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// Design Name:
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// Module Name: DDS_compensate
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module DDS_compensate(
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clk,
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rst,
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din_nd, // 输入数据
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din_i,
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din_q,
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acq_nd, // 捕获信息
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dfreq_word_nd, // 频偏NCO信息
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dfreq_word,
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framesync_success, // 帧同步标志，用于切码
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// rs_idx_nd, //数据段信息速率，在帧同步标志后、勤务段最后一个数据前给出，！但并不表示从rs_idx_nd有效起输入就是数据段的数据了
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// rs_idx,
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demod_trunc_i,
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demod_trunc_q,
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demod_trunc_nd,
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Demod_ovrflw
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);
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input clk;
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input rst;
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input din_nd;
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input [11:0] din_i,din_q;
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input acq_nd;
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input dfreq_word_nd;
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input [13:0] dfreq_word; //-- 解调频偏
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input framesync_success;
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//-- 8个可变数据速率，从0~7分别代表30k~3840k
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wire rs_idx_nd =1'b0;
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wire [2:0] rs_idx;
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assign rs_idx =3'b000;
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output [11:0] demod_trunc_i,demod_trunc_q;
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output demod_trunc_nd ;
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output Demod_ovrflw;
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wire [4:0] acq_freindex; //-- 捕获频偏
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assign acq_freindex =5'd0;
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//----------------------------- DDS For FreqShift --------------------------------
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//-- 注意这里DDS产生的是偏移频率，下面补偿的时候要与DDS输出的【共轭】相复乘
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localparam DDS_width = 24; //25bits in fact
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reg dds_rst = 0; // DDS starts after acquisition
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reg [DDS_width:0] dds_start_freq = 0;
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reg dds_update = 0; // identifier of updated deltafrequency & its rate
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reg [DDS_width:0] dds_update_df = 0;
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reg [DDS_width:0] dds_phase = 0;
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reg [DDS_width:0] dds_freq = 0; // 相位累积量，残余频偏和变化率控制
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/*wire [13:0] freq_abs;
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reg freq_plus;
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assign freq_abs=(dfreq_word[13]==1'd1)? -dfreq_word:dfreq_word;
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always @ (posedge clk) begin
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if(rst) begin
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freq_plus <= 1'b0;
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end
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else begin
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if(dfreq_word_nd) begin
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freq_plus <= dfreq_word[13];
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end
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else begin
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freq_plus <= freq_plus;
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end
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end
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end
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*/
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always @(posedge clk)
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if (rst || acq_nd)
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dds_rst <= 1;
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else
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dds_rst <= 0;
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always @(posedge clk)
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if (!rst && acq_nd)
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dds_start_freq <= {{8{acq_freindex[4]}},acq_freindex[4:0],{(DDS_width-12){1'b0}}};
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else
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dds_start_freq <= dds_start_freq;
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always @(posedge clk)
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if (!rst && dfreq_word_nd) begin
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dds_update <= 1;
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dds_update_df <= {{(DDS_width-13){dfreq_word[13]}},dfreq_word[13:0]};
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end
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else
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dds_update <= 0;
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always @(posedge clk)
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if (rst || dds_rst)
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dds_phase <= 0;
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else if (din_nd)
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dds_phase <= dds_phase + dds_freq;
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else
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dds_phase <= dds_phase;
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wire [DDS_width:0] updata_s;
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AdderSigned_25_25_2dly DDS_DFreq_Update1 (
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//.A(dds_freq), // input wire [24 : 0] A
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.A(25'd0),
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.B(dds_update_df), // input wire [24 : 0] B
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.CLK(clk), // input wire CLK
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.S(updata_s) // output wire [24 : 0] S
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);
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//--- delay ---
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reg dds_update_d1 = 0,dds_update_d2 = 0;
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reg din_nd_d1 = 0,din_nd_d2 = 0;
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always @(posedge clk)
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if (rst) begin
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dds_update_d1 <= 0;
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dds_update_d2 <= 0;
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din_nd_d1 <= 0;
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din_nd_d2 <= 0;
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end
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else begin
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dds_update_d1 <= dds_update;
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dds_update_d2 <= dds_update_d1;
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din_nd_d1 <= din_nd;
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din_nd_d2 <= din_nd_d1;
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end
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always @(posedge clk)
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if (rst)
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dds_freq <= 0;
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else if (dds_rst)
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dds_freq <= dds_start_freq;
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else if (dds_update_d2)
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dds_freq <= updata_s;
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else
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dds_freq <= dds_freq;
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reg [12:0] cos_addr = 0,sin_addr = -13'd2048;
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wire [11:0] cos_dout,sin_dout;
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always @(posedge clk)
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if (rst) begin
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cos_addr <= 0;
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sin_addr <= -13'd2048;
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end
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else begin
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cos_addr <= dds_phase[DDS_width:DDS_width-12];
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sin_addr <= dds_phase[DDS_width:DDS_width-12] - 13'd2048;
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end
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COSLUT_8192 DDS_12bit_8192 (
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.clka(clk), // input wire clka
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.addra(cos_addr), // input wire [12 : 0] addra
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.douta(cos_dout), // output wire [11 : 0] douta
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.clkb(clk), // input wire clkb
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.addrb(sin_addr), // input wire [12 : 0] addrb
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.doutb(sin_dout) // output wire [11 : 0] doutb
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);
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//------------------------------- Compensate ------------------------------
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wire [24:0] demod_i,demod_q;
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wire [13:0] DemodMult_pad;
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//wire [11:0] demod_trunc_i,demod_trunc_q;
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wire demod_nd; //排除第一个，这两个信号和din_nd是同步的
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//wire demod_trunc_nd;
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wire Demod_ovrflw_i,Demod_ovrflw_q;
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//wire Demod_ovrflw ;
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assign Demod_ovrflw = Demod_ovrflw_i || Demod_ovrflw_q;
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/*wire [11:0] sin_din;
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wire [11:0] cos_din;
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assign sin_din=(freq_plus==1'd1)? sin_dout:-sin_dout;
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assign cos_din = cos_dout;*/
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ComplexMult12x12_4dly MultFreq (
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.aclk(clk), // input wire aclk
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.s_axis_a_tvalid(din_nd), // input wire s_axis_a_tvalid
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.s_axis_a_tdata({4'd0,din_q,4'd0,din_i}), // input wire [31 : 0] s_axis_a_tdata
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.s_axis_b_tvalid(din_nd), // input wire s_axis_b_tvalid
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.s_axis_b_tdata({4'd0,-sin_dout,4'd0,cos_dout}), // input wire [15 : 0] s_axis_b_tdata
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.m_axis_dout_tvalid(demod_nd), // output wire m_axis_dout_tvalid
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.m_axis_dout_tdata({DemodMult_pad[13:7],demod_q,DemodMult_pad[6:0],demod_i}) // output wire [47 : 0] m_axis_dout_tdata
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);
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trunc_25to12_2dly Trunc_demod_i (
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.clk(clk),
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.din_nd(demod_nd),
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.din(demod_i),
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.ctrl(),
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.dout_nd(demod_trunc_nd),
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.dout(demod_trunc_i),
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.ovrflw(Demod_ovrflw_i)
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);
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trunc_25to12_2dly Trunc_demod_q (
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.clk(clk),
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.din_nd(demod_nd),
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.din(demod_q),
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.ctrl(),
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.dout_nd(),
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.dout(demod_trunc_q),
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.ovrflw(Demod_ovrflw_q)
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);
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endmodule
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