974 lines
30 KiB
Verilog
974 lines
30 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/11/14 17:44:48
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// Design Name:
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// Module Name: FrameMerge
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module FrameMerge(
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input clk,
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input rst,
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input rst2,
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input sync,
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input nd,
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input din,
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input [6:0] vio_stopbit,
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input frameIDnd,
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input clk2,
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output reg framerdy = 1'b0,
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// output reg flag_recvram = 1'b0,
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// input [12:0] recv_addr1,
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// input [12:0] recv_addr2,
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// output [7:0] recv_data1,
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// output [7:0] recv_data2,
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input [13:0] recv_addr_new_0,
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input [13:0] recv_addr_new_1,
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input [13:0] recv_addr_new_2,
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input [13:0] recv_addr_new_3,
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output [7:0] recv_data_new_0,
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output [7:0] recv_data_new_1,
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output [7:0] recv_data_new_2,
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output [7:0] recv_data_new_3,
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output reg [16:0] RAMaddra_write_0 = 17'd0,
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output reg [16:0] RAMaddra_write_1 = 17'd0,
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output reg [16:0] RAMaddra_write_2 = 17'd0,
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output reg [16:0] RAMaddra_write_3 = 17'd0,
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output reg [16:0] RAMaddra_new_0 = 17'd0,
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output reg [16:0] RAMaddra_new_1 = 17'd0,
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output reg [16:0] RAMaddra_new_2 = 17'd0,
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output reg [16:0] RAMaddra_new_3 = 17'd0,
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output reg flag_notbyte = 1'd0,
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output reg [1:0] state_ram = 2'd0,
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output reg flag_stop = 1'd0, //给shx，拉高一个clk表示当前时帧有效数据接收完毕
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output reg [16:0] addr_stop = 17'd0, //给shx，拉高一个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
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//debug
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output reg berstart_1d = 1'b0,
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output reg bercompare = 1'b0,
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output reg [16:0] bercount = 17'd0,
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output reg [16:0] bercount_max = 17'd0,
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output reg [16:0] ROMaddra_d2 = 17'd0,
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output reg RAMdout_d1 = 1'd0,
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// output reg validnd_1_1d = 1'b0,
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// output reg validnd_2_1d = 1'b0,
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output reg validnd_new_new = 1'b0,
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// output reg [63:0] stop_temp_1 = 64'd0,
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// output reg [63:0] stop_temp_2 = 64'd0,
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output reg [63:0] stop_temp_new = 64'd0,
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output flag_stop_0, //给shx，拉高1个clk表示当前时帧有效数据接收完毕
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output [16:0] addr_stop_0,
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output reg [2:0] cnt_8 = 3'b0,
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output reg state_8 = 1'd0,
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output rdy_scramble,
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output dout_scramble,
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output reg [16:0] RAMaddra = 17'd0, //比较误码率
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output reg [16:0] ROMaddra = 17'd0, //比较误码率
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output reg [0:0] nd_ber = 1'd0, //比较误码率
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output reg [63:0] recvNetData,
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output reg recvNetDataNd
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// input [7:0] video_id01,
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// input [7:0] video_id02,
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// input [7:0] video_id03,
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// input [7:0] MAC_idNum
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);
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reg frameIDnd_d1 = 1'd0;
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reg frameIDnd_d2 = 1'd0;
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always @(posedge clk)begin
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frameIDnd_d1 <= frameIDnd;
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frameIDnd_d2 <= frameIDnd_d1;
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end
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// always @(posedge clk)begin
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// if(frameIDnd && !frameIDnd_d1) flag_recvram <= ~flag_recvram;
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// else flag_recvram <= flag_recvram;
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// end
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//-------------------------------------------------------------------------------------------------------------//
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// reg validnd_1 = 1'b0;
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// reg validnd_2 = 1'b0;
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reg validnd_new = 1'b0;
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reg [9:0] validlength = 10'd0;
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reg [6:0] cnt_net;
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reg [1:0] state_recv;
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reg nd_recvnet_dout;
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always @(posedge clk)begin
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if(rst)begin
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// validnd_1 <= 1'b0;
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// validnd_2 <= 1'b0;
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state_recv <= 2'd0;
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validnd_new <= 1'b0;
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validlength <= 10'd0;
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cnt_net <= 6'd0;
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nd_recvnet_dout <= 1'd0;
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end
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else begin
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case(state_recv)
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2'd0:begin
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if(!validnd_new)begin
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if(sync)begin
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validnd_new <= 1'b1;
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nd_recvnet_dout <= 1'b1;
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end
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else begin
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validnd_new <= 1'b0;
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end
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end
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else begin
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if(cnt_net == 6'd63) begin
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validlength <= validlength + 10'd1;
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if(validlength == 10'd1023)begin
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validnd_new <= 1'b0;
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state_recv <= 2'd1;
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end else begin
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validnd_new <= 1'b1;
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state_recv <= state_recv;
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end
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nd_recvnet_dout <= 1'b0;
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cnt_net <= 6'd63;
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end
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else begin
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state_recv <= state_recv;
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nd_recvnet_dout <= 1'b1;
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cnt_net <= cnt_net +6'd1;
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validlength <= validlength + 10'd1;
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if(validlength == 10'd1023)begin
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validnd_new <= 1'b0;
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end else begin
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validnd_new <= 1'b1;
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end
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end
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end
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end
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2'd1:begin
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if(!validnd_new)begin
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if(sync)begin
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validnd_new <= 1'b1;
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end
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else begin
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validnd_new <= 1'b0;
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end
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state_recv <= state_recv;
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end
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else begin
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state_recv <= state_recv;
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nd_recvnet_dout <= 1'b0;
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cnt_net <= 6'd0;
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validlength <= validlength + 10'd1;
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if(validlength == 10'd1023)begin
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validnd_new <= 1'b0;
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end else begin
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validnd_new <= 1'b1;
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end
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end
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end
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default:begin
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if(!validnd_new)begin
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if(sync)begin
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validnd_new <= 1'b1;
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nd_recvnet_dout <= 1'b1;
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end
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else begin
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validnd_new <= 1'b0;
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end
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end
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else begin
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if(cnt_net == 6'd63) begin
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validlength <= validlength + 10'd1;
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if(validlength == 10'd1023)begin
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validnd_new <= 1'b0;
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state_recv <= 2'd1;
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end else begin
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validnd_new <= 1'b1;
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state_recv <= state_recv;
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end
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nd_recvnet_dout <= 1'b0;
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cnt_net <= 6'd63;
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end
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else begin
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state_recv <= state_recv;
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nd_recvnet_dout <= 1'b1;
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cnt_net <= cnt_net +6'd1;
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validlength <= validlength + 10'd1;
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if(validlength == 10'd1023)begin
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validnd_new <= 1'b0;
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end else begin
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validnd_new <= 1'b1;
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end
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end
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end
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end
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endcase
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end
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end
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// reg [15:0] RAMaddra_1 = 16'd0;
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// reg [15:0] RAMaddra_2 = 16'd0;
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// reg [16:0] RAMaddra_new = 17'd0;
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// reg [15:0] RAMaddra = 16'd0; //比较误码率
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reg [0:0] dout_scramble_d1 = 1'd0; //比较误码率
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// reg [0:0] nd_ber = 1'd0; //比较误码率
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// reg validnd_1_1d = 1'b0;
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// reg validnd_2_1d = 1'b0;
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reg validnd_new_1d = 1'b0;
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always @(posedge clk)begin
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if(rst)begin
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// RAMaddra_1 <= 16'd0;
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// RAMaddra_2 <= 16'd0;
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// RAMaddra_new <= RAMaddra_new;
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RAMaddra <= 17'd0; //比较误码率
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ROMaddra <= 17'd0; //比较误码率
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dout_scramble_d1 <= 1'd0; //比较误码率
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nd_ber <= 1'd0; //比较误码率
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// validnd_1_1d <= 1'b0;
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// validnd_2_1d <= 1'b0;
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validnd_new_1d <= 1'b0;
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end else begin
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// validnd_1_1d <= validnd_1;
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// if(validnd_1_1d) begin
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// RAMaddra_1 <= RAMaddra_1 + 16'd1;
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// end else begin
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// RAMaddra_1 <= RAMaddra_1;
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// end
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// validnd_2_1d <= validnd_2;
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// if(validnd_2_1d) begin
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// RAMaddra_2 <= RAMaddra_2 + 16'd1;
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// end else begin
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// RAMaddra_2 <= RAMaddra_2;
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// end
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validnd_new_1d <= validnd_new;
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// if(validnd_new_1d) begin
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// RAMaddra_new <= RAMaddra_new + 16'd1;
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// end else begin
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// RAMaddra_new <= RAMaddra_new;
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// end
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//比较误码率
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// if(validnd_1_1d||validnd_2_1d) begin
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if(validnd_new_1d) begin
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RAMaddra <= RAMaddra + 17'd1;
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ROMaddra <= ROMaddra + 17'd1;
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dout_scramble_d1 <= dout_scramble;
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nd_ber <= 1'd1;
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end
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else begin
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RAMaddra <= RAMaddra;
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ROMaddra <= ROMaddra;
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dout_scramble_d1 <= dout_scramble_d1;
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nd_ber <= 1'd0;
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end
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//比较误码率
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end
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end
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reg nd_recvnet_dout_d1;
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reg nd_recvnet_dout_d2;
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reg nd_recvnet_dout_d3;
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reg nd_recvnet_dout_d4;
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reg wr_en_232;
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reg rs232_send;
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reg [4:0] cnt_422_wait;
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wire validnd_new_delay;
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reg validnd_new_delay_d1;
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wire framedata;
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reg framedata_d1;
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reg [7:0] data_net_byte [87:0];
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reg [7:0] clk_net_byte;
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reg [9:0] clk_net_bit;
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//shiftram_scramble shiftram_scramble(.CLK(clk),.D({dout_scramble,validnd_new}),.Q({framedata,validnd_new_delay}));
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reg [7:0] cnt_422_net;
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always @(posedge clk)begin
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if(rst2)begin
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state_ram <= 2'd0;
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RAMaddra_new_0 <= 17'd0;
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RAMaddra_new_1 <= 17'd0;
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RAMaddra_new_2 <= 17'd0;
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RAMaddra_new_3 <= 17'd0;
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flag_notbyte <= 1'd0;
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nd_recvnet_dout_d1 <= 1'd0;
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nd_recvnet_dout_d2 <= 1'd0;
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nd_recvnet_dout_d3 <= 1'd0;
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nd_recvnet_dout_d4 <= 1'd0;
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recvNetDataNd <= 1'd0;
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recvNetData <= 64'd0;
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wr_en_232 <= 1'b0;
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rs232_send <= 1'b0;
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cnt_422_wait <= 5'd0;
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cnt_422_net <= 8'd0;
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clk_net_bit <= 10'd0;
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clk_net_byte <= 8'd0;
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validnd_new_delay_d1 <= 1'b0;
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framedata_d1 <= 1'b0;
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end
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else begin
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framedata_d1 <= framedata;
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validnd_new_delay_d1 <= validnd_new_delay;
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nd_recvnet_dout_d1 <= nd_recvnet_dout;
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nd_recvnet_dout_d2 <= nd_recvnet_dout_d1;
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nd_recvnet_dout_d3 <= nd_recvnet_dout_d2;
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nd_recvnet_dout_d4 <= nd_recvnet_dout_d3;
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if(!nd_recvnet_dout_d1 && nd_recvnet_dout_d2) begin//检测到网络层数据传输完毕拉高2个clk recvNetDataNd
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recvNetDataNd <= 1'b1;
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end
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else begin
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if(!nd_recvnet_dout_d3 && nd_recvnet_dout_d4) begin//延迟2个clk确保50MHz采到recvNetDataNd再拉低
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recvNetDataNd <= 1'b0;
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end
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else begin
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recvNetDataNd <= recvNetDataNd;
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end
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end
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case(state_ram)
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//有了新的一帧，准备开始存储
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2'd0:begin
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if(frameIDnd_d2) begin
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state_ram <= 2'd1;
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RAMaddra_new_0<= RAMaddra_new_0;
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RAMaddra_new_1<= RAMaddra_new_1;
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RAMaddra_new_2 <= RAMaddra_new_2;
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RAMaddra_new_3 <= RAMaddra_new_3;
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end
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else begin
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state_ram <= state_ram;
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RAMaddra_new_0<= RAMaddra_new_0;
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RAMaddra_new_1<= RAMaddra_new_1;
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RAMaddra_new_2 <= RAMaddra_new_2;
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RAMaddra_new_3 <= RAMaddra_new_3;
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end
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validnd_new_new <= 1'd0;
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flag_notbyte <= 1'd0;
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end
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2'd1:begin
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if(flag_stop_0) begin
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if(recvNetData[63:56] == 8'd2 && recvNetData[23:0]==24'h7E5A33) begin
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RAMaddra_new_0 <= addr_stop_0 +17'd1;
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end
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else if(recvNetData[63:56] == 8'd3 && recvNetData[23:0]==24'h7E5A33) begin
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RAMaddra_new_1 <= addr_stop_0 +17'd1;
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end
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else if(recvNetData[63:56] == 8'd4 && recvNetData[23:0]==24'h7E5A33) begin
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RAMaddra_new_2 <= addr_stop_0 +17'd1;
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end
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else if(recvNetData[63:56] == 8'hff && recvNetData[23:0]==24'h7E5A33) begin
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RAMaddra_new_3 <= addr_stop_0 +17'd1;
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end
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else begin
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RAMaddra_new_0 <= RAMaddra_new_0;
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RAMaddra_new_1 <= RAMaddra_new_1;
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RAMaddra_new_2 <= RAMaddra_new_2;
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RAMaddra_new_3 <= RAMaddra_new_3;
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end
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validnd_new_new <= 1'd0;
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state_ram <= 2'd2;
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end
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else begin
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state_ram <= state_ram;
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validnd_new_new <= validnd_new;
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if(validnd_new_new) begin
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if(nd_recvnet_dout_d1) begin
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recvNetData[63:0] <= {dout_scramble,recvNetData[63:1]};
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end
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else begin
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if(recvNetData[63:56] == 8'd2 && recvNetData[23:0]==24'h7E5A33) begin
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RAMaddra_new_0 <= RAMaddra_new_0 + 17'd1;
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RAMaddra_new_1 <= RAMaddra_new_1;
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RAMaddra_new_2 <= RAMaddra_new_2;
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RAMaddra_new_3 <= RAMaddra_new_3;
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end
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else if(recvNetData[63:56] == 8'd3 && recvNetData[23:0]==24'h7E5A33) begin
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RAMaddra_new_0 <= RAMaddra_new_0;
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RAMaddra_new_1 <= RAMaddra_new_1 + 17'd1;
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RAMaddra_new_2 <= RAMaddra_new_2;
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RAMaddra_new_3 <= RAMaddra_new_3;
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end
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else if(recvNetData[63:56] == 8'd4 && recvNetData[23:0]==24'h7E5A33) begin
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RAMaddra_new_0 <= RAMaddra_new_0;
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RAMaddra_new_1 <= RAMaddra_new_1;
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RAMaddra_new_2 <= RAMaddra_new_2 + 17'd1;
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RAMaddra_new_3 <= RAMaddra_new_3;
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end
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else if(recvNetData[63:56] == 8'hff && recvNetData[23:0]==24'h7E5A33) begin
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RAMaddra_new_0 <= RAMaddra_new_0;
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RAMaddra_new_1 <= RAMaddra_new_1;
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RAMaddra_new_2 <= RAMaddra_new_2;
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RAMaddra_new_3 <= RAMaddra_new_3 + 17'd1;
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end
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else begin
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RAMaddra_new_0 <= RAMaddra_new_0;
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RAMaddra_new_1 <= RAMaddra_new_1;
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RAMaddra_new_2 <= RAMaddra_new_2;
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RAMaddra_new_3 <= RAMaddra_new_3;
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end
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end
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end
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else begin
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RAMaddra_new_0 <= RAMaddra_new_0;
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RAMaddra_new_1 <= RAMaddra_new_1;
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RAMaddra_new_2 <= RAMaddra_new_2;
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RAMaddra_new_3 <= RAMaddra_new_3;
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end
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end
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flag_notbyte <= 1'd0;
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end
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2'd2:begin
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// rs232_send <= 1'b0;
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state_ram <= 2'd0;
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if(recvNetData[63:56] == 8'd2 && recvNetData[23:0]==24'h7E5A33) begin
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case(RAMaddra_new_0[2:0])
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3'b000:begin
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flag_notbyte <= 1'd0;
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RAMaddra_new_0 <= RAMaddra_new_0;
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end
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3'b001:begin
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flag_notbyte <= 1'd1;
|
|
RAMaddra_new_0 <= RAMaddra_new_0+17'd7;
|
|
end
|
|
3'b010:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_0 <= RAMaddra_new_0+17'd6;
|
|
end
|
|
3'b011:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_0 <= RAMaddra_new_0+17'd5;
|
|
end
|
|
3'b100:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_0 <= RAMaddra_new_0+17'd4;
|
|
end
|
|
3'b101:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_0 <= RAMaddra_new_0+17'd3;
|
|
end
|
|
3'b110:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_0 <= RAMaddra_new_0+17'd2;
|
|
end
|
|
3'b111:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_0 <= RAMaddra_new_0+17'd1;
|
|
end
|
|
endcase
|
|
end
|
|
else if(recvNetData[63:56] == 8'd3 && recvNetData[23:0]==24'h7E5A33) begin
|
|
case(RAMaddra_new_1[2:0])
|
|
3'b000:begin
|
|
flag_notbyte <= 1'd0;
|
|
RAMaddra_new_1 <= RAMaddra_new_1;
|
|
end
|
|
3'b001:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_1 <= RAMaddra_new_1+17'd7;
|
|
end
|
|
3'b010:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_1 <= RAMaddra_new_1+17'd6;
|
|
end
|
|
3'b011:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_1 <= RAMaddra_new_1+17'd5;
|
|
end
|
|
3'b100:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_1 <= RAMaddra_new_1+17'd4;
|
|
end
|
|
3'b101:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_1 <= RAMaddra_new_1+17'd3;
|
|
end
|
|
3'b110:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_1 <= RAMaddra_new_1+17'd2;
|
|
end
|
|
3'b111:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_1 <= RAMaddra_new_1+17'd1;
|
|
end
|
|
endcase
|
|
end
|
|
else if(recvNetData[63:56] == 8'd4 && recvNetData[23:0]==24'h7E5A33) begin
|
|
case(RAMaddra_new_2[2:0])
|
|
3'b000:begin
|
|
flag_notbyte <= 1'd0;
|
|
RAMaddra_new_2 <= RAMaddra_new_2;
|
|
end
|
|
3'b001:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_2 <= RAMaddra_new_2+17'd7;
|
|
end
|
|
3'b010:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_2 <= RAMaddra_new_2+17'd6;
|
|
end
|
|
3'b011:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_2 <= RAMaddra_new_2+17'd5;
|
|
end
|
|
3'b100:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_2 <= RAMaddra_new_2+17'd4;
|
|
end
|
|
3'b101:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_2 <= RAMaddra_new_2+17'd3;
|
|
end
|
|
3'b110:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_2 <= RAMaddra_new_2+17'd2;
|
|
end
|
|
3'b111:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_2 <= RAMaddra_new_2+17'd1;
|
|
end
|
|
endcase
|
|
end
|
|
else if(recvNetData[63:56] == 8'hff&& recvNetData[23:0]==24'h7E5A33) begin
|
|
case(RAMaddra_new_3[2:0])
|
|
3'b000:begin
|
|
flag_notbyte <= 1'd0;
|
|
RAMaddra_new_3 <= RAMaddra_new_3;
|
|
end
|
|
3'b001:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_3 <= RAMaddra_new_3+17'd7;
|
|
end
|
|
3'b010:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_3 <= RAMaddra_new_3+17'd6;
|
|
end
|
|
3'b011:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_3 <= RAMaddra_new_3+17'd5;
|
|
end
|
|
3'b100:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_3 <= RAMaddra_new_3+17'd4;
|
|
end
|
|
3'b101:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_3 <= RAMaddra_new_3+17'd3;
|
|
end
|
|
3'b110:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_3 <= RAMaddra_new_3+17'd2;
|
|
end
|
|
3'b111:begin
|
|
flag_notbyte <= 1'd1;
|
|
RAMaddra_new_3 <= RAMaddra_new_3+17'd1;
|
|
end
|
|
endcase
|
|
end
|
|
else begin
|
|
flag_notbyte <= 1'b0;
|
|
RAMaddra_new_0 <= RAMaddra_new_0;
|
|
RAMaddra_new_1 <= RAMaddra_new_1;
|
|
RAMaddra_new_2 <= RAMaddra_new_2;
|
|
RAMaddra_new_3 <= RAMaddra_new_3;
|
|
end
|
|
|
|
end
|
|
default:begin
|
|
if(frameIDnd_d2) begin
|
|
state_ram <= 2'd1;
|
|
RAMaddra_new_0 <= RAMaddra_new_0;
|
|
RAMaddra_new_1 <= RAMaddra_new_1;
|
|
RAMaddra_new_2 <= RAMaddra_new_2;
|
|
RAMaddra_new_3 <= RAMaddra_new_3;
|
|
end
|
|
else begin
|
|
state_ram <= state_ram;
|
|
RAMaddra_new_0 <= RAMaddra_new_0;
|
|
RAMaddra_new_1 <= RAMaddra_new_1;
|
|
RAMaddra_new_2 <= RAMaddra_new_2;
|
|
RAMaddra_new_3 <= RAMaddra_new_3;
|
|
end
|
|
validnd_new_new <= 1'd0;
|
|
flag_notbyte <= 1'd0;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
|
|
reg [8:0] bagcnt = 9'd0;
|
|
always @(posedge clk)begin
|
|
if(rst)begin
|
|
bagcnt <= 9'd0;
|
|
end else begin
|
|
if(sync)begin
|
|
bagcnt <= bagcnt + 9'd1;
|
|
end else begin
|
|
bagcnt <= bagcnt;
|
|
end
|
|
end
|
|
end
|
|
|
|
wire scramblestart;
|
|
assign scramblestart = (bagcnt == 9'd0)? sync : 1'b0;
|
|
|
|
// wire rdy_scramble;
|
|
// wire dout_scramble;
|
|
Scramble Scramble (
|
|
.clk(clk),
|
|
.rst(rst2 || framerdy),
|
|
.start(scramblestart),
|
|
// .nd(validnd_1||validnd_2),
|
|
.nd(validnd_new),
|
|
.din(din),
|
|
.rdy(rdy_scramble),
|
|
.dout(dout_scramble)
|
|
);
|
|
|
|
|
|
|
|
//------------------------------------------比较误码率---------------------------//
|
|
reg [16:0] RAMaddrb = 17'd0;
|
|
wire RAMdout;
|
|
RAM_merge RAM_merge_0 (
|
|
.clka(clk), // input clka
|
|
// .wea(validnd_1_1d||validnd_2_1d), // input [0 : 0] wea
|
|
.wea(validnd_new_1d), // input [0 : 0] wea
|
|
.addra(RAMaddra), // input [16 : 0] addra
|
|
.dina(dout_scramble), // input [0 : 0] dina
|
|
.clkb(clk), // input clkb
|
|
.addrb(RAMaddrb), // input [16 : 0] addrb
|
|
.doutb(RAMdout) // output [0 : 0] doutb
|
|
);
|
|
|
|
// reg [15:0] ROMaddra = 16'd0;
|
|
wire ROMdout;
|
|
ROM_ber ROM_ber (
|
|
.clka(clk), // input clka
|
|
.addra(ROMaddra), // input [16 : 0] addra
|
|
.douta(ROMdout) // output [0 : 0] douta
|
|
);
|
|
|
|
reg berstart = 1'b0;
|
|
always @(posedge clk)begin
|
|
if(rst2)begin
|
|
RAMaddrb <= 17'd0;
|
|
berstart <= 1'b0;
|
|
end else begin
|
|
if(!berstart)begin
|
|
RAMaddrb <= 17'd0;
|
|
if(bagcnt == 9'd105 && validlength == 10'd1023)begin
|
|
berstart <= 1'b1;
|
|
end else begin
|
|
berstart <= 1'b0;
|
|
end
|
|
end else begin
|
|
if(RAMaddrb == 17'd107519)begin
|
|
berstart <= 1'b0;
|
|
RAMaddrb <= 17'd0;
|
|
end else begin
|
|
berstart <= 1'b1;
|
|
RAMaddrb <= RAMaddrb + 17'd1;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
|
|
|
|
|
|
reg [16:0] ROMaddra_d1 = 17'd0;
|
|
always @(posedge clk)begin
|
|
berstart_1d <= berstart;
|
|
if(rst)begin
|
|
bercompare <= 1'b0;
|
|
bercount <= 17'd0;
|
|
ROMaddra_d1 <= 17'd0;
|
|
ROMaddra_d2 <= 17'd0;
|
|
RAMdout_d1 <= 1'd0;
|
|
bercount_max <= bercount;
|
|
end else begin
|
|
if(nd_ber) begin
|
|
bercompare <= dout_scramble_d1^ROMdout;
|
|
bercount <= bercount + bercompare;
|
|
|
|
ROMaddra_d1 <= ROMaddra;
|
|
ROMaddra_d2 <= ROMaddra_d1;
|
|
RAMdout_d1 <= dout_scramble_d1;
|
|
bercount_max <= bercount_max;
|
|
end
|
|
else begin
|
|
bercompare <= 1'd0;
|
|
bercount <= bercount;
|
|
|
|
ROMaddra_d1 <= ROMaddra_d1;
|
|
ROMaddra_d2 <= ROMaddra_d2;
|
|
RAMdout_d1 <= RAMdout_d1;
|
|
bercount_max <= bercount_max;
|
|
end
|
|
end
|
|
end
|
|
//------------------------------------------比较误码率---------------------------//
|
|
|
|
|
|
|
|
// RAM_recv RAM_recv_1 (
|
|
// .clka(clk), // input clka
|
|
// .wea(validnd_1_1d), // input [0 : 0] wea
|
|
// .addra(RAMaddra_1), // input [15 : 0] addra
|
|
// .dina(dout_scramble), // input [0 : 0] dina
|
|
// .clkb(clk2), // input clkb
|
|
// .addrb(recv_addr1), // input [12 : 0] addrb
|
|
// .doutb(recv_data1) // output [7 : 0] doutb
|
|
// );
|
|
|
|
// RAM_recv RAM_recv_2 (
|
|
// .clka(clk), // input clka
|
|
// .wea(validnd_2_1d), // input [0 : 0] wea
|
|
// .addra(RAMaddra_2), // input [15 : 0] addra
|
|
// .dina(dout_scramble), // input [0 : 0] dina
|
|
// .clkb(clk2), // input clkb
|
|
// .addrb(recv_addr2), // input [12 : 0] addrb
|
|
// .doutb(recv_data2) // output [7 : 0] doutb
|
|
// );
|
|
|
|
RAM_recvnew RAM_recvnew_0 (
|
|
.clka(clk), // input clka
|
|
.wea(validnd_new_new), // input [0 : 0] wea
|
|
.addra(RAMaddra_new_0), // input [16 : 0] addra
|
|
.dina(dout_scramble), // input [0 : 0] dina
|
|
.clkb(clk2), // input clkb
|
|
.addrb(recv_addr_new_0), // input [13 : 0] addrb
|
|
.doutb(recv_data_new_0) // output [7 : 0] doutb
|
|
);
|
|
|
|
RAM_recvnew RAM_recvnew_1 (
|
|
.clka(clk), // input clka
|
|
.wea(validnd_new_new), // input [0 : 0] wea
|
|
.addra(RAMaddra_new_1), // input [16 : 0] addra
|
|
.dina(dout_scramble), // input [0 : 0] dina
|
|
.clkb(clk2), // input clkb
|
|
.addrb(recv_addr_new_1), // input [13 : 0] addrb
|
|
.doutb(recv_data_new_1) // output [7 : 0] doutb
|
|
);
|
|
RAM_recvnew RAM_recvnew_2 (
|
|
.clka(clk), // input clka
|
|
.wea(validnd_new_new), // input [0 : 0] wea
|
|
.addra(RAMaddra_new_2), // input [16 : 0] addra
|
|
.dina(dout_scramble), // input [0 : 0] dina
|
|
.clkb(clk2), // input clkb
|
|
.addrb(recv_addr_new_2), // input [13 : 0] addrb
|
|
.doutb(recv_data_new_2) // output [7 : 0] doutb
|
|
);
|
|
/*RAM_recvnew RAM_recvnew_3 (
|
|
.clka(clk), // input clka
|
|
.wea(validnd_new_new), // input [0 : 0] wea
|
|
.addra(RAMaddra_new_3), // input [16 : 0] addra
|
|
.dina(dout_scramble), // input [0 : 0] dina
|
|
.clkb(clk2), // input clkb
|
|
.addrb(recv_addr_new_3), // input [13 : 0] addrb
|
|
.doutb(recv_data_new_3) // output [7 : 0] doutb
|
|
);*/
|
|
|
|
//-------------------------------------------------------------------------------------------------------------//
|
|
|
|
//-------------------------------------找停止位---------------------------//
|
|
|
|
|
|
// reg nd_stop_1 = 1'd0;
|
|
// reg nd_stop_2 = 1'd0;
|
|
reg nd_stop_new = 1'd0;
|
|
|
|
// reg [15:0] RAMaddra_1_temp = 16'd0;
|
|
// reg [15:0] RAMaddra_2_temp = 16'd0;
|
|
reg [16:0] RAMaddra_new_temp = 17'd0;
|
|
find_stop find_stop (
|
|
.clk(clk),
|
|
// .nd_stop_1(nd_stop_1),
|
|
// .nd_stop_2(nd_stop_2),
|
|
.nd_stop_new(nd_stop_new),
|
|
// .RAMaddra_1_temp(RAMaddra_1_temp),
|
|
// .RAMaddra_2_temp(RAMaddra_2_temp),
|
|
.RAMaddra_new_temp(RAMaddra_new_temp),
|
|
// .stop_temp_1(stop_temp_1),
|
|
// .stop_temp_2(stop_temp_2),
|
|
.stop_temp_new(stop_temp_new),
|
|
|
|
.vio_stopbit(vio_stopbit),
|
|
|
|
.flag_stop_0(flag_stop_0),
|
|
.addr_stop_0(addr_stop_0)
|
|
);
|
|
|
|
// reg [63:0] stop_temp_1 = 64'd0;
|
|
// reg [63:0] stop_temp_2 = 64'd0;
|
|
// reg flag_stop_0 = 1'd0; //给shx，拉高1个clk表示当前时帧有效数据接收完毕
|
|
// reg [15:0] addr_stop_0 = 16'd0; //给shx，拉高1个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
|
|
always @(posedge clk)begin
|
|
// nd_stop_1 <= validnd_1_1d;
|
|
// nd_stop_2 <= validnd_2_1d;
|
|
nd_stop_new <= validnd_new_1d;
|
|
// if(validnd_1_1d) begin
|
|
// stop_temp_1[0] <= dout_scramble;
|
|
// stop_temp_1[63:1] <= stop_temp_1[62:0];
|
|
// RAMaddra_1_temp <= RAMaddra_1;
|
|
// RAMaddra_2_temp <= 16'd0;
|
|
// end
|
|
// else begin
|
|
// if(validnd_2_1d) begin
|
|
// stop_temp_2[0] <= dout_scramble;
|
|
// stop_temp_2[63:1] <= stop_temp_2[62:0];
|
|
// RAMaddra_1_temp <= 16'd0;
|
|
// RAMaddra_2_temp <= RAMaddra_2;
|
|
// end
|
|
// else begin
|
|
// stop_temp_1 <= stop_temp_1;
|
|
// stop_temp_2 <= stop_temp_2;
|
|
|
|
// RAMaddra_1_temp <= RAMaddra_1_temp;
|
|
// RAMaddra_2_temp <= RAMaddra_2_temp;
|
|
// end
|
|
// end
|
|
if(validnd_new_1d) begin
|
|
stop_temp_new[0] <= dout_scramble;
|
|
stop_temp_new[63:1] <= stop_temp_new[62:0];
|
|
if(recvNetData[63:56] == 8'd2 && recvNetData[23:0]==24'h7E5A33) begin
|
|
RAMaddra_new_temp <= RAMaddra_new_0;
|
|
end
|
|
else if(recvNetData[63:56] == 8'd3 && recvNetData[23:0]==24'h7E5A33) begin
|
|
RAMaddra_new_temp <= RAMaddra_new_1;
|
|
end
|
|
else if(recvNetData[63:56] == 8'd4 && recvNetData[23:0]==24'h7E5A33) begin
|
|
RAMaddra_new_temp <= RAMaddra_new_2;
|
|
end
|
|
else if(recvNetData[63:56] == 8'hff && recvNetData[23:0]==24'h7E5A33) begin
|
|
RAMaddra_new_temp <= RAMaddra_new_3;
|
|
end
|
|
else begin
|
|
RAMaddra_new_temp <= RAMaddra_new_temp;
|
|
end
|
|
end
|
|
else begin
|
|
stop_temp_new <= stop_temp_new;
|
|
|
|
RAMaddra_new_temp <= RAMaddra_new_temp;
|
|
end
|
|
end
|
|
|
|
|
|
// reg [2:0] cnt_8 = 3'b0;
|
|
// reg state_8 = 1'd0;
|
|
always @(posedge clk)begin
|
|
case(state_8)
|
|
1'd0:begin
|
|
if(flag_stop_0)begin
|
|
cnt_8 <= 3'b0;
|
|
flag_stop <= 1'b1;
|
|
addr_stop <= addr_stop_0;
|
|
state_8 <= 1'd1;
|
|
end
|
|
else begin
|
|
cnt_8 <= 3'b0;
|
|
flag_stop <= 1'b0;
|
|
addr_stop <= addr_stop;
|
|
state_8 <= state_8;
|
|
end
|
|
end
|
|
1'd1:begin
|
|
if(cnt_8==3'd7) begin
|
|
cnt_8 <= 3'b0;
|
|
flag_stop <= 1'b0;
|
|
addr_stop <= addr_stop;
|
|
state_8 <= 1'd0;
|
|
end
|
|
else begin
|
|
cnt_8 <= 3'b1+cnt_8;
|
|
flag_stop <= 1'b1;
|
|
addr_stop <= addr_stop;
|
|
state_8 <= state_8;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
|
|
|
|
reg [16:0] RAMaddra_new_0_d1 = 17'd0;
|
|
reg [16:0] RAMaddra_new_1_d1 = 17'd0;
|
|
reg [16:0] RAMaddra_new_2_d1 = 17'd0;
|
|
reg [16:0] RAMaddra_new_3_d1 = 17'd0;
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always@(posedge clk2)begin
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|
RAMaddra_new_0_d1 <= RAMaddra_new_0;
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|
RAMaddra_new_1_d1 <= RAMaddra_new_1;
|
|
RAMaddra_new_2_d1 <= RAMaddra_new_2;
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|
RAMaddra_new_3_d1 <= RAMaddra_new_3;
|
|
RAMaddra_write_0 <= RAMaddra_new_0_d1;
|
|
RAMaddra_write_1 <= RAMaddra_new_1_d1;
|
|
RAMaddra_write_2 <= RAMaddra_new_2_d1;
|
|
RAMaddra_write_3 <= RAMaddra_new_3_d1;
|
|
end
|
|
|
|
//-------------------------------------找停止位---------------------------//
|
|
|
|
|
|
|
|
always @(posedge clk)begin
|
|
if(rst2)begin
|
|
framerdy <= 1'b0;
|
|
end else begin
|
|
if(bagcnt == 9'd105 && validlength == 10'd1023)begin
|
|
framerdy <= 1'b1;
|
|
end else begin
|
|
framerdy <= 1'b0;
|
|
end
|
|
end
|
|
end
|
|
|
|
ila_ber ila_ber(
|
|
.clk(clk),
|
|
.probe0(rst),
|
|
.probe1(ROMdout),
|
|
.probe2(validnd_new_delay),
|
|
.probe3(bercount),
|
|
.probe4(flag_stop_0),
|
|
.probe5(framedata_d1),
|
|
.probe6(recvNetDataNd),
|
|
.probe7(addr_stop_0),
|
|
.probe8(nd_recvnet_dout_d1),
|
|
.probe9(recvNetData),
|
|
.probe10(dout_scramble),
|
|
.probe11(wr_en_232),
|
|
.probe12(framedata),
|
|
.probe13(data_net_byte[87]),
|
|
.probe14(RAMaddra_new_0),
|
|
.probe15(RAMaddra_new_1)
|
|
|
|
);
|
|
|
|
|
|
endmodule
|
|
|