150 lines
2.8 KiB
Verilog
150 lines
2.8 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 16:01:14 07/21/2018
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// Design Name:
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// Module Name: IQmerge
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module IQmerge(
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input clk,
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input clk2,
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input rst,
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input nd,
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input framesync,
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input [9:0] dini,
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input [9:0] dinq,
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output reg rdy = 1'b0,
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output reg ldpcsyncin = 1'b0,
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output [7:0] dout
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);
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reg [9:0] addra = 10'd0;
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reg [15:0] dina = 16'd0;
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reg [10:0] addrb = 11'd0;
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RAM_IQmerge RAM_IQmerge (
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.clka(clk), // input clka
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.wea(1'b1), // input [0 : 0] wea
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.addra(addra), // input [9 : 0] addra
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.dina(dina), // input [15 : 0] dina
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.clkb(clk2), // input clkb
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.addrb(addrb), // input [10 : 0] addrb
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.doutb(dout) // output [7 : 0] doutb
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);
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reg [9:0] addradelay = 10'd0;
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reg [8:0] bagcount = 9'd0;
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reg [1:0] writevalid = 2'd0;
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always @(posedge clk)begin
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if(rst)begin
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addra <= 10'd0;
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addradelay <= 10'd0;
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dina <= 16'd0;
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writevalid <= 2'd0;
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bagcount <= 9'd0;
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end else begin
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case(writevalid)
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2'd0:begin
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if(framesync)begin
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writevalid <= 2'd1;
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end else begin
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writevalid <= 2'd0;
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end
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bagcount <= 9'd0;
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end
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2'd1:begin
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if(nd)begin
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addradelay <= addradelay + 10'd1;
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dina <= {dinq[9:2],dini[9:2]};
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addra <= addradelay;
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if(addradelay == 10'd1023)begin
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writevalid <= 2'd2;
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end else begin
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writevalid <= 2'd1;
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end
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end else begin
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addradelay <= addradelay;
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addra <= addra;
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dina <= dina;
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writevalid <= 2'd1;
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end
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end
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2'd2:begin
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bagcount <= bagcount + 9'd1;
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if(bagcount == 9'd104)begin
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writevalid <= 2'd0;
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end else begin
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writevalid <= 2'd1;
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end
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end
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default:writevalid <= 2'd0;
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endcase
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end
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end
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reg readvalid = 1'b0;
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always @(posedge clk2)begin
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if(rst)begin
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addrb <= 11'd0;
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readvalid <= 1'b0;
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ldpcsyncin <= 1'b0;
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end else begin
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if(!readvalid)begin
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addrb <= 11'd0;
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if(addra == 10'd1000)begin
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ldpcsyncin <= 1'b1;
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readvalid <= 1'b1;
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end else begin
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ldpcsyncin <= 1'b0;
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readvalid <= 1'b0;
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end
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end else begin
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ldpcsyncin <= 1'b0;
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addrb <= addrb + 11'd1;
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if(addrb == 11'd2047)begin
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readvalid <= 1'b0;
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end else begin
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readvalid <= 1'b1;
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end
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end
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end
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end
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always @(posedge clk2)begin
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rdy <= readvalid;
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end
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/*ila_IQmerge ila_IQmerge(
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.clk(clk2),
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.probe0(clk),
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.probe1(writevalid),
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.probe2(dini[9:2]),
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.probe3(dinq[9:2]),
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.probe4(dout),
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.probe5(framesync)
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);*/
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endmodule
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