70 lines
1.6 KiB
Verilog
70 lines
1.6 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/11/18 21:06:38
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// Design Name:
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// Module Name: Interp_quarter
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module Interp_quarter(
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input clk,
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input [9:0] din_p1,
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input [9:0] din_t0,
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input [9:0] din_n1,
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input [9:0] din_n2,
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output reg [9:0] dout
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);
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wire [13:0] multquartern2;
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wire [15:0] multquartern1;
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wire [16:0] multquartert0;
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wire [13:0] multquarterp1;
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CN2 CN2_quarter (.CLK(clk), .A(din_p1), .P(multquartern2));
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CN1 CN1_quarter (.CLK(clk), .A(din_t0), .P(multquartern1));
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CT0 CT0_quarter (.CLK(clk), .A(din_n1), .P(multquartert0));
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CP1 CP1_quarter (.CLK(clk), .A(din_n2), .P(multquarterp1));
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reg [16:0] sumquarter1 = 17'd0;
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reg [17:0] sumquarter2 = 18'd0;
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always @(posedge clk)begin
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sumquarter1 <= {{3{multquartern2[13]}},multquartern2}+{multquartern1[15],multquartern1};
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sumquarter2 <= {{4{multquarterp1[13]}},multquarterp1}+{multquartert0[16],multquartert0};
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end
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reg [18:0] sumquarter3 = 19'd0;
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always @(posedge clk)begin
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sumquarter3 <= {{2{sumquarter1[16]}},sumquarter1}+{sumquarter2[17],sumquarter2};
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end
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always @(posedge clk)begin
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if(sumquarter3[18:16]==3'b111||sumquarter3[18:16]==3'b000)begin
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dout <= sumquarter3[16:7];
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end else begin
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dout <= (sumquarter3[18]==1'b1) ? 10'b10_0000_0000 : 10'b01_1111_1111;
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end
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end
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endmodule
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