101 lines
2.7 KiB
Verilog
101 lines
2.7 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/11/18 21:03:55
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// Design Name:
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// Module Name: Interpolation
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module Interpolation(
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input clk,
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input [9:0] dini,
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input [9:0] dinq,
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input framesync,
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output reg framesync_Interpolation = 1'd0,
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output reg [9:0] doutiA = 10'd0,
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output reg [9:0] doutqA = 10'd0,
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output [9:0] doutiB,
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output [9:0] doutqB,
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output [9:0] doutiC,
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output [9:0] doutqC,
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output [9:0] doutiD,
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output [9:0] doutqD
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);
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reg [9:0] dini_p1 = 10'd0;
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reg [9:0] dini_t0 = 10'd0;
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reg [9:0] dini_n1 = 10'd0;
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reg [9:0] dini_n2 = 10'd0;
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reg [9:0] dini_n3 = 10'd0;
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reg [9:0] dini_n4 = 10'd0;
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reg [9:0] dinq_p1 = 10'd0;
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reg [9:0] dinq_t0 = 10'd0;
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reg [9:0] dinq_n1 = 10'd0;
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reg [9:0] dinq_n2 = 10'd0;
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reg [9:0] dinq_n3 = 10'd0;
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reg [9:0] dinq_n4 = 10'd0;
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reg [0:0] framesync_p1 = 1'd0;
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reg [0:0] framesync_t0 = 1'd0;
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reg [0:0] framesync_n1 = 1'd0;
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reg [0:0] framesync_n2 = 1'd0;
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reg [0:0] framesync_n3 = 1'd0;
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reg [0:0] framesync_n4 = 1'd0;
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always @(posedge clk)begin
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dini_p1 <= dini;
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dini_t0 <= dini_p1;
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dini_n1 <= dini_t0;
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dini_n2 <= dini_n1;
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dini_n3 <= dini_n2;
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dini_n4 <= dini_n3;
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doutiA <= dini_n4;
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dinq_p1 <= dinq;
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dinq_t0 <= dinq_p1;
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dinq_n1 <= dinq_t0;
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dinq_n2 <= dinq_n1;
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dinq_n3 <= dinq_n2;
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dinq_n4 <= dinq_n3;
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doutqA <= dinq_n4;
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framesync_p1 <= framesync;
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framesync_t0 <= framesync_p1;
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framesync_n1 <= framesync_t0;
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framesync_n2 <= framesync_n1;
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framesync_n3 <= framesync_n2;
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framesync_n4 <= framesync_n3;
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framesync_Interpolation <= framesync_n4;
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end
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Interp_quarter Interp_quarteri (.clk(clk), .din_p1(dini_p1), .din_t0(dini_t0), .din_n1(dini_n1), .din_n2(dini_n2), .dout(doutiB));
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Interp_quarter Interp_quarterq (.clk(clk), .din_p1(dinq_p1), .din_t0(dinq_t0), .din_n1(dinq_n1), .din_n2(dinq_n2), .dout(doutqB));
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Interp_half Interp_halfi (.clk(clk), .din_p1(dini_p1), .din_t0(dini_t0), .din_n1(dini_n1), .din_n2(dini_n2), .dout(doutiC));
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Interp_half Interp_halfq (.clk(clk), .din_p1(dinq_p1), .din_t0(dinq_t0), .din_n1(dinq_n1), .din_n2(dinq_n2), .dout(doutqC));
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Interp_quarter Interp_quarteri3 (.clk(clk), .din_p1(dini_n2), .din_t0(dini_n1), .din_n1(dini_t0), .din_n2(dini_p1), .dout(doutiD));
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Interp_quarter Interp_quarterq3 (.clk(clk), .din_p1(dinq_n2), .din_t0(dinq_n1), .din_n1(dinq_t0), .din_n2(dinq_p1), .dout(doutqD));
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endmodule
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