122 lines
3.8 KiB
Verilog
122 lines
3.8 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 17:44 11/14/2019
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// Design Name:
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// Module Name: MF_Top
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module MF_Top (
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input clk,
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input rst,
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input [11:0] dini,
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input [11:0] dinq,
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input start,
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output reg [9:0] matchfilterout_i = 10'd0,
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output reg [9:0] matchfilterout_q = 10'd0,
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output reg MF_rdy,
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output reg MF_rst
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);
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wire s_axis_data_tvalid_i;
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wire s_axis_data_tready_i;
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wire m_axis_data_tvalid_i;
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wire [31:0] MF_m_axis_data_tdata_i;
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assign s_axis_data_tvalid_i = start;
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MF12p5_12bit MF12p5_12bit_i (
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.aclk (clk), // input wire aclk
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.s_axis_data_tvalid(s_axis_data_tvalid_i), // input wire s_axis_data_tvalid
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.s_axis_data_tready(s_axis_data_tready_i), // output wire s_axis_data_tready
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.s_axis_data_tdata ({4'd0, dini}), // input wire [15 : 0] s_axis_data_tdata
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.m_axis_data_tvalid(m_axis_data_tvalid_i), // output wire m_axis_data_tvalid
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.m_axis_data_tdata (MF_m_axis_data_tdata_i) // output wire [31 : 0] m_axis_data_tdata
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);
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wire s_axis_data_tvalid_q;
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wire s_axis_data_tready_q;
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wire m_axis_data_tvalid_q;
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wire [31:0] MF_m_axis_data_tdata_q;
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assign s_axis_data_tvalid_q = start;
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MF12p5_12bit MF12p5_12bit_q (
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.aclk (clk), // input wire aclk
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.s_axis_data_tvalid(s_axis_data_tvalid_q), // input wire s_axis_data_tvalid
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.s_axis_data_tready(s_axis_data_tready_q), // output wire s_axis_data_tready
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.s_axis_data_tdata ({4'd0, dinq}), // input wire [15 : 0] s_axis_data_tdata
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.m_axis_data_tvalid(m_axis_data_tvalid_q), // output wire m_axis_data_tvalid
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.m_axis_data_tdata (MF_m_axis_data_tdata_q) // output wire [31 : 0] m_axis_data_tdata
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);
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//截位：结果为MF_m_axis_data_tdata_i/q[25:0]
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//低位截位15bit，高位截位1bit，得10bit宽结果
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always @(posedge clk) begin
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if (MF_m_axis_data_tdata_i[25:24] == 2'b00 || MF_m_axis_data_tdata_i[25:24] == 2'b11) begin
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matchfilterout_i <= MF_m_axis_data_tdata_i[24:15];
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end
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else begin
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matchfilterout_i <= (MF_m_axis_data_tdata_i[25] == 1'b1) ? 10'b10_0000_0000 : 10'b01_1111_1111;
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end
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if (MF_m_axis_data_tdata_q[25:24] == 2'b00 || MF_m_axis_data_tdata_q[25:24] == 2'b11) begin
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matchfilterout_q <= MF_m_axis_data_tdata_q[24:15];
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end
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else begin
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matchfilterout_q <= (MF_m_axis_data_tdata_q[25] == 1'b1) ? 10'b10_0000_0000 : 10'b01_1111_1111;
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end
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end
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reg MF_rdy_d1;
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always @(posedge clk) begin
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MF_rdy_d1 <= MF_rdy;
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if (rst) begin
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MF_rdy <= 1'b0;
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MF_rst <= 1'b0;
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end
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else begin
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MF_rdy <= start;
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if ((MF_rdy == 1'b1) && (MF_rdy_d1 == 1'b0)) begin
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MF_rst <= 1'b1;
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end
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else begin
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MF_rst <= 1'b0;
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end
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end
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end
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//------DEBUG模块------//
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`ifdef MF_debug
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//ILA
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/*ila_16x8 ila_MF_inst(
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.clk(clk),
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.probe0(dini),
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.probe1(dinq),
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.probe2(start),
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.probe3(matchfilterout_i),
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.probe4(matchfilterout_q),
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.probe5(MF_rdy),
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.probe6(8'b0),
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.probe7(8'b0)
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);*/
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`endif
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endmodule
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