61 lines
2.2 KiB
Verilog
61 lines
2.2 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 21:27:25 01/18/2018
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// Design Name:
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// Module Name: Normalization_Factor_0_8125
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module Normalization_Factor_0_8125 #(
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parameter WIDTH = 4'd8
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) (
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input clk,
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input [WIDTH-1:0] din_NF, //输入为非负数
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output reg [WIDTH-1:0] dout_NF = 8'd0 //输出相对输入延时3个时钟周期
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);
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reg [WIDTH-1:0] din_NF_reg0 = 8'd0, din_NF_reg1 = 8'd0;
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reg [WIDTH-1:0] sum_1 = 8'd0, sum_2 = 8'd0;
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always @(posedge clk) begin
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din_NF_reg0 <= din_NF;
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din_NF_reg1 <= din_NF_reg0;
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end
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always @(posedge clk) begin //对输入数据乘以系数0.8125
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sum_1 <= (din_NF >> 1) + (din_NF >> 2);
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sum_2 <= sum_1 + (din_NF_reg0 >> 4);
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case ({
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din_NF_reg1[3:0]
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}) //matlab中用round函数，verilog中默认是floor函数
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4'b0000: dout_NF <= sum_2 + 8'd0;
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4'b0001: dout_NF <= sum_2 + 8'd1;
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4'b0010: dout_NF <= sum_2 + 8'd1;
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4'b0011: dout_NF <= sum_2 + 8'd1;
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4'b0100: dout_NF <= sum_2 + 8'd0;
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4'b0101: dout_NF <= sum_2 + 8'd1;
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4'b0110: dout_NF <= sum_2 + 8'd1; //32个数，0~15和16~31的数是一样的，所以用din_NF_reg1&4'b1111，
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4'b0111: dout_NF <= sum_2 + 8'd2; //例如，din_NF_reg1=6'd19,经过din_NF_reg1&4'b1111之后，变成了6'd3
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4'b1000: dout_NF <= sum_2 + 8'd1;
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4'b1001: dout_NF <= sum_2 + 8'd1;
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4'b1010: dout_NF <= sum_2 + 8'd1;
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4'b1011: dout_NF <= sum_2 + 8'd2;
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4'b1100: dout_NF <= sum_2 + 8'd1;
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4'b1101: dout_NF <= sum_2 + 8'd2;
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4'b1110: dout_NF <= sum_2 + 8'd1;
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4'b1111: dout_NF <= sum_2 + 8'd2;
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default: dout_NF <= 8'd0;
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endcase
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end
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endmodule
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