560 lines
26 KiB
Verilog
560 lines
26 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/12/18 16:00:24
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// Design Name:
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// Module Name: SC_FDE_TOP
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module SC_FDE_TOP (
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input clk,
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input rst,
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input EQUenable_vio, //为1时启用均衡
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input [7:0] Zerozone_vio, //零域估计，默认值为8'd29
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input flag_ow_left, //在一帧内，与第一个数据段的pilot的ow第一个nd对齐
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input nd,
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input [9:0] dini,
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input [9:0] dinq,
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output nd_SC_FDE_dout,
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output [9:0] SC_FDE_douti,
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output [9:0] SC_FDE_doutq,
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// debug,溢出标志
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output flagoverflow_fftpilot_26to14, //第1个fft结果截位，即导频fft结果的截位，26截到14
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output flagoverflow_ChnZF_26to18, //第2个fft结果截位，即ZF信道估计结果的截位，26截到18
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output flagoverflow_comdiv_34to20i, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18
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output flagoverflow_comdiv_34to20q, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18
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output flagoverflow_ifftzero_29to17i, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
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output flagoverflow_ifftzero_29to17q, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
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output flagoverflow_MMSEdiv_divisor_31to28, //第2个除法器，即MMSE除法的分母截位，31截到28
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output flagoverflow_divmmse_34to11, //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11
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output flagoverflow_ifftindata_28to20i, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
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output flagoverflow_ifftindata_28to20q, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
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output flagoverflow_fftdata_26to16i, //数据段ow的fft输出截位，26截到16
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output flagoverflow_fftdata_26to16q, //数据段ow的fft输出截位，26截到16
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output flagoverflow_FDE_dataout_29to10i, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
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output flagoverflow_FDE_dataout_29to10q //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
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);
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//-----------------------------------------导频和数据ow的缓存--------------------------------------------//
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//----------------------还负责计算正负导频头的和与差。流水得到结果用于信道估计----------------------------//
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//数据的fifo，4个
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wire [9:0] din_data1i;
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wire [9:0] din_data1q;
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wire wr_en_data1;
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wire [9:0] din_data2i;
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wire [9:0] din_data2q;
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wire wr_en_data2;
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wire flag_dataow; //拉高1clk，说明一段数据ow存储完毕，后端可开始连续读取
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wire flag_ChnEstFFT_done; //信道估计两次fft输入完毕后拉高1clk(Chn_Estimate给出)
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//正负导频段的加减结果
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wire nd_pilot2;
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wire [9:0] pilot_datai;
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wire [9:0] pilot_dataq;
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wire [9:0] pilot_noisei;
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wire [9:0] pilot_noiseq;
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data_ow data_ow_djy (
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.clk (clk),
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.rst (rst),
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.flag_ow_left(flag_ow_left),
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.nd (nd),
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.dini (dini),
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.dinq (dinq),
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.din_data1i (din_data1i),
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.din_data1q (din_data1q),
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.wr_en_data1(wr_en_data1),
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.din_data2i (din_data2i),
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.din_data2q (din_data2q),
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.wr_en_data2(wr_en_data2),
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.flag_dataow(flag_dataow), //拉高1clk，说明一段数据ow存储完毕，后端可开始连续读取
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.nd_pilot2 (nd_pilot2),
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.pilot_datai (pilot_datai),
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.pilot_dataq (pilot_dataq),
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.pilot_noisei(pilot_noisei),
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.pilot_noiseq(pilot_noiseq)
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);
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//-------------------------------------------data数据ow的fifo，4个--------------------------------------------//
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wire rd_en_data1;
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wire [9:0] dout_data1i;
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wire full_data1i;
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wire empty_data1i;
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fifo_ow256 fifo_data_ow1i (
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.rst (rst), // input wire rst
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.wr_clk(clk), // input wire wr_clk
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.rd_clk(clk), // input wire rd_clk
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.din (din_data1i), // input wire [9 : 0] din
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.wr_en (wr_en_data1), // input wire wr_en
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.rd_en (rd_en_data1), // input wire rd_en
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.dout (dout_data1i), // output wire [9 : 0] dout
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.full (full_data1i), // output wire full
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.empty (empty_data1i) // output wire empty
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);
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wire [9:0] dout_data1q;
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wire full_data1q;
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wire empty_data1q;
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fifo_ow256 fifo_data_ow1q (
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.rst (rst), // input wire rst
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.wr_clk(clk), // input wire wr_clk
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.rd_clk(clk), // input wire rd_clk
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.din (din_data1q), // input wire [9 : 0] din
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.wr_en (wr_en_data1), // input wire wr_en
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.rd_en (rd_en_data1), // input wire rd_en
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.dout (dout_data1q), // output wire [9 : 0] dout
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.full (full_data1q), // output wire full
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.empty (empty_data1q) // output wire empty
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);
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wire rd_en_data2;
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wire [9:0] dout_data2i;
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wire full_data2i;
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wire empty_data2i;
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fifo_ow256 fifo_data_ow2i (
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.rst (rst), // input wire rst
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.wr_clk(clk), // input wire wr_clk
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.rd_clk(clk), // input wire rd_clk
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.din (din_data2i), // input wire [9 : 0] din
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.wr_en (wr_en_data2), // input wire wr_en
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.rd_en (rd_en_data2), // input wire rd_en
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.dout (dout_data2i), // output wire [9 : 0] dout
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.full (full_data2i), // output wire full
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.empty (empty_data2i) // output wire empty
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);
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wire [9:0] dout_data2q;
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wire full_data2q;
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wire empty_data2q;
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fifo_ow256 fifo_data_ow2q (
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.rst (rst), // input wire rst
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.wr_clk(clk), // input wire wr_clk
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.rd_clk(clk), // input wire rd_clk
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.din (din_data2q), // input wire [9 : 0] din
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.wr_en (wr_en_data2), // input wire wr_en
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.rd_en (rd_en_data2), // input wire rd_en
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.dout (dout_data2q), // output wire [9 : 0] dout
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.full (full_data2q), // output wire full
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.empty (empty_data2q) // output wire empty
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);
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//-----------------------------------------------------噪声估计--------------------------------------------------//
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//--------------------------------------------噪声估计结果放大了256*49倍-----------------------------------------//
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//噪声估计结果
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wire nd_EstNoise;
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wire [27:0] EstNoise_i;
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wire [27:0] EstNoise_q;
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Noise_Estimate Noise_Estimate_djy (
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.clk(clk),
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.rst(rst),
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.nd_pilot2 (nd_pilot2),
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.pilot_noisei(pilot_noisei),
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.pilot_noiseq(pilot_noiseq),
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.nd_EstNoise(nd_EstNoise),
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.EstNoise_i (EstNoise_i),
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.EstNoise_q (EstNoise_q)
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);
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//------------------------------------------fft核，及其输入输出控制器------------------------------------------//
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reg fft_config_tvalid = 1'd0;
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wire fft_config_tready;
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reg [16:0] fft_in_i = 17'd0;
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reg [16:0] fft_in_q = 17'd0;
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reg fft_in_nd = 1'd0;
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wire fft_in_tready;
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wire [63:0] fft_out_tdata;
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wire [25:0] fft_out_i;
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wire [25:0] fft_out_q;
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wire fft_out_nd;
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wire [ 7:0] fft_index;
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assign fft_out_i = fft_out_tdata[25:0];
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assign fft_out_q = fft_out_tdata[57:32];
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wire m_axis_data_tlast;
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wire event_frame_started;
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wire event_tlast_unexpected;
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wire event_tlast_missing;
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wire event_status_channel_halt;
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wire event_data_in_channel_halt;
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wire event_data_out_channel_halt;
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fft_256 fft_256 (
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.aclk (clk), // input wire aclk
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.aresetn (~rst), // input wire aresetn低有效复位，每次帧结束后复位8clk，满足核要求
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.s_axis_config_tdata (8'd1), // input wire [7 : 0] s_axis_config_tdata
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.s_axis_config_tvalid (fft_config_tvalid), // input wire s_axis_config_tvalid
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.s_axis_config_tready (fft_config_tready), // output wire s_axis_config_tready
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// s data
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.s_axis_data_tdata ({7'd0, fft_in_q, 7'd0, fft_in_i}), // input wire [47 : 0] s_axis_data_tdata
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.s_axis_data_tvalid (fft_in_nd), // input wire s_axis_data_tvalid
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.s_axis_data_tready (fft_in_tready), // output wire s_axis_data_tready
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.s_axis_data_tlast (1'd0), // input wire s_axis_data_tlastn不用给这个信号
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// m data
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.m_axis_data_tdata (fft_out_tdata), // output wire [63 : 0] m_axis_data_tdata
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.m_axis_data_tuser (fft_index), // output wire [7 : 0] m_axis_data_tuser
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.m_axis_data_tvalid (fft_out_nd), // output wire m_axis_data_tvalid
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.m_axis_data_tready (1'd1), // input wire m_axis_data_tready
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.m_axis_data_tlast (m_axis_data_tlast), // output wire m_axis_data_tlast
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//flag
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.event_frame_started (event_frame_started), // output wire event_frame_started
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.event_tlast_unexpected (event_tlast_unexpected), // output wire event_tlast_unexpected
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.event_tlast_missing (event_tlast_missing), // output wire event_tlast_missing
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.event_status_channel_halt (event_status_channel_halt), // output wire event_status_channel_halt
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.event_data_in_channel_halt (event_data_in_channel_halt), // output wire event_data_in_channel_halt
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.event_data_out_channel_halt(event_data_out_channel_halt) // output wire event_data_out_channel_halt
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);
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reg [ 1:0] state_fft = 2'd0;
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wire nd_pilotfft;
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wire [16:0] fft_in_i_pilot;
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wire [16:0] fft_in_q_pilot;
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wire nd_datafft;
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wire [16:0] fft_in_i_data;
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wire [16:0] fft_in_q_data;
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always @(posedge clk) begin
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if (rst) begin
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fft_config_tvalid <= 1'd0;
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fft_in_i <= 17'd0;
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fft_in_q <= 17'd0;
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fft_in_nd <= 1'd0;
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state_fft <= 2'd0;
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end
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else begin
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case (state_fft)
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//帧间复位结束后，先等待fft_config_tvalid拉高，说明fft核允许配置，先写入一次fft配置
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2'd0: begin
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if (fft_config_tready) begin
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fft_config_tvalid <= 1'd1;
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fft_in_nd <= 1'd0;
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state_fft <= state_fft + 2'd1;
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end
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else begin
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fft_config_tvalid <= 1'd0;
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fft_in_nd <= 1'd0;
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state_fft <= state_fft;
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end
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end
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//每帧一开始fft核输入交给信道估计模块，直到flag_ChnEstFFT_done到来，说明信道估计两次fft输入完毕(Chn_Estimate给出)
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2'd1: begin
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fft_config_tvalid <= 1'd0;
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if (flag_ChnEstFFT_done) begin
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fft_in_i <= fft_in_i_data;
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fft_in_q <= fft_in_q_data;
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fft_in_nd <= nd_datafft;
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state_fft <= state_fft + 2'd1;
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end
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else begin
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fft_in_i <= fft_in_i_pilot;
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fft_in_q <= fft_in_q_pilot;
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fft_in_nd <= nd_pilotfft;
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state_fft <= state_fft;
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end
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end
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//nd_pilot2拉高，说明下一个征服导频头处理完毕，fft输入控制权交还信道估计模块
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2'd2: begin
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fft_config_tvalid <= 1'd0;
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if (nd_pilot2) begin
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fft_in_i <= fft_in_i_pilot;
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fft_in_q <= fft_in_q_pilot;
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fft_in_nd <= nd_pilotfft;
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state_fft <= 2'd1;
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end
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else begin
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fft_in_i <= fft_in_i_data;
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fft_in_q <= fft_in_q_data;
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fft_in_nd <= nd_datafft;
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state_fft <= state_fft;
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end
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end
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default: state_fft <= 2'd0;
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endcase
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end
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end
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//------------------------------------------ifft核，及其输入输出控制器------------------------------------------//
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reg ifft_config_tvalid = 1'd0;
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wire ifft_config_tready;
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reg [19:0] ifft_in_i = 20'd0;
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reg [19:0] ifft_in_q = 20'd0;
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reg ifft_in_nd = 1'd0;
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wire ifft_in_tready;
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wire [63:0] ifft_out_tdata;
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wire [28:0] ifft_out_i;
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wire [28:0] ifft_out_q;
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wire ifft_out_nd;
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wire [ 7:0] ifft_index;
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assign ifft_out_i = ifft_out_tdata[28:0];
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assign ifft_out_q = ifft_out_tdata[60:32];
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wire m_axis_data_tlast_ifft;
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wire event_frame_started_ifft;
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wire event_tlast_unexpected_ifft;
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wire event_tlast_missing_ifft;
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wire event_status_channel_halt_ifft;
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wire event_data_in_channel_halt_ifft;
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wire event_data_out_channel_halt_ifft;
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ifft_256 ifft_256 (
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.aclk (clk), // input wire aclk
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.aresetn(~rst), // input wire aresetn
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.s_axis_config_tdata (8'd0), // input wire [7 : 0] s_axis_config_tdata
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.s_axis_config_tvalid(ifft_config_tvalid), // input wire s_axis_config_tvalid
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.s_axis_config_tready(ifft_config_tready), // output wire s_axis_config_tready
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.s_axis_data_tdata ({4'd0, ifft_in_q, 4'd0, ifft_in_i}), // input wire [47 : 0] s_axis_data_tdata
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.s_axis_data_tvalid(ifft_in_nd), // input wire s_axis_data_tvalid
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.s_axis_data_tready(ifft_in_tready), // output wire s_axis_data_tready
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.s_axis_data_tlast (1'd0), // input wire s_axis_data_tlast
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.m_axis_data_tdata (ifft_out_tdata), // output wire [63 : 0] m_axis_data_tdata
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.m_axis_data_tuser (ifft_index), // output wire [7 : 0] m_axis_data_tuser
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.m_axis_data_tvalid(ifft_out_nd), // output wire m_axis_data_tvalid
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.m_axis_data_tready(1'd1), // input wire m_axis_data_tready
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.m_axis_data_tlast (m_axis_data_tlast_ifft), // output wire m_axis_data_tlast
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.event_frame_started (event_frame_started_ifft), // output wire event_frame_started
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.event_tlast_unexpected (event_tlast_unexpected_ifft), // output wire event_tlast_unexpected
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.event_tlast_missing (event_tlast_missing_ifft), // output wire event_tlast_missing
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.event_status_channel_halt (event_status_channel_halt_ifft), // output wire event_status_channel_halt
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.event_data_in_channel_halt (event_data_in_channel_halt_ifft), // output wire event_data_in_channel_halt
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.event_data_out_channel_halt(event_data_out_channel_halt_ifft) // output wire event_data_out_channel_halt
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);
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reg [ 1:0] state_ifft = 2'd0;
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wire nd_pilotifft;
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wire [19:0] ifft_in_i_pilot;
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wire [19:0] ifft_in_q_pilot;
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wire nd_dataifft;
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wire [19:0] ifft_in_i_data;
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wire [19:0] ifft_in_q_data;
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always @(posedge clk) begin
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if (rst) begin
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ifft_config_tvalid <= 1'd0;
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ifft_in_i <= 20'd0;
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ifft_in_q <= 20'd0;
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ifft_in_nd <= 1'd0;
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state_ifft <= 2'd0;
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end
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else begin
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case (state_ifft)
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//帧间复位结束后，先等待ifft_config_tvalid拉高，说明ifft核允许配置，先写入一次ifft配置
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2'd0: begin
|
||
if (ifft_config_tready) begin
|
||
ifft_config_tvalid <= 1'd1;
|
||
ifft_in_nd <= 1'd0;
|
||
state_ifft <= state_ifft + 2'd1;
|
||
end
|
||
else begin
|
||
ifft_config_tvalid <= 1'd0;
|
||
ifft_in_nd <= 1'd0;
|
||
state_ifft <= state_ifft;
|
||
end
|
||
end
|
||
//每帧一开始ifft核输入交给信道估计模块，直到flag_ChnEstFFT_done到来，说明信道估计两次fft输入完毕(Chn_Estimate给出)
|
||
2'd1: begin
|
||
ifft_config_tvalid <= 1'd0;
|
||
if (flag_ChnEstFFT_done) begin
|
||
ifft_in_i <= ifft_in_i_data;
|
||
ifft_in_q <= ifft_in_q_data;
|
||
ifft_in_nd <= nd_dataifft;
|
||
state_ifft <= state_ifft + 2'd1;
|
||
end
|
||
else begin
|
||
ifft_in_i <= ifft_in_i_pilot;
|
||
ifft_in_q <= ifft_in_q_pilot;
|
||
ifft_in_nd <= nd_pilotifft;
|
||
state_ifft <= state_ifft;
|
||
end
|
||
end
|
||
//nd_pilot2拉高，说明下一个征服导频头处理完毕，ifft输入控制权交还信道估计模块
|
||
2'd2: begin
|
||
ifft_config_tvalid <= 1'd0;
|
||
if (nd_pilot2) begin
|
||
ifft_in_i <= ifft_in_i_pilot;
|
||
ifft_in_q <= ifft_in_q_pilot;
|
||
ifft_in_nd <= nd_pilotifft;
|
||
state_ifft <= 2'd1;
|
||
end
|
||
else begin
|
||
ifft_in_i <= ifft_in_i_data;
|
||
ifft_in_q <= ifft_in_q_data;
|
||
ifft_in_nd <= nd_dataifft;
|
||
state_ifft <= state_ifft;
|
||
end
|
||
end
|
||
default: state_ifft <= 2'd0;
|
||
endcase
|
||
end
|
||
end
|
||
|
||
|
||
//----------------------------------------------------MMSE信道估计结果RAM--------------------------------------------------//
|
||
wire write_MMSE_wea;
|
||
wire [ 7:0] addrin_MMSE;
|
||
wire [ 7:0] addrout_MMSE;
|
||
wire [21:0] din_MMSE;
|
||
wire [21:0] dout_MMSE;
|
||
|
||
RAM_ChnEst_MMSE RAM_ChnEst_MMSE (
|
||
.clka (clk), // input wire clka
|
||
.wea (write_MMSE_wea), // input wire [0 : 0] wea
|
||
.addra(addrin_MMSE), // input wire [7 : 0] addra
|
||
.dina (din_MMSE), // input wire [21 : 0] dina
|
||
.clkb (clk), // input wire clkb
|
||
.addrb(addrout_MMSE), // input wire [7 : 0] addrb
|
||
.doutb(dout_MMSE) // output wire [21 : 0] doutb
|
||
);
|
||
|
||
//----------------------------------------------------MMSE信道估计模块--------------------------------------------------//
|
||
Chn_Estimate Chn_Estimate_djy (
|
||
.clk (clk),
|
||
.rst (rst),
|
||
//零域估计，默认值为8'd29
|
||
.Zerozone_vio (Zerozone_vio),
|
||
//增强导频序列
|
||
.nd_pilot2 (nd_pilot2),
|
||
.pilot_datai (pilot_datai),
|
||
.pilot_dataq (pilot_dataq),
|
||
//噪声估计结果
|
||
.nd_EstNoise (nd_EstNoise),
|
||
.EstNoise_i (EstNoise_i),
|
||
.EstNoise_q (EstNoise_q),
|
||
//fft核
|
||
.fft_out_i (fft_out_i),
|
||
.fft_out_q (fft_out_q),
|
||
.fft_out_nd (fft_out_nd),
|
||
.fft_index (fft_index),
|
||
.fft_in_i (fft_in_i_pilot),
|
||
.fft_in_q (fft_in_q_pilot),
|
||
.fft_in_nd (nd_pilotfft),
|
||
//ifft核
|
||
.ifft_out_i (ifft_out_i),
|
||
.ifft_out_q (ifft_out_q),
|
||
.ifft_out_nd (ifft_out_nd),
|
||
.ifft_index (ifft_index),
|
||
.ifft_in_i (ifft_in_i_pilot),
|
||
.ifft_in_q (ifft_in_q_pilot),
|
||
.ifft_in_nd (nd_pilotifft),
|
||
//信道估计两次fft输入完毕后拉高1clk
|
||
.flag_ChnEstFFT_done (flag_ChnEstFFT_done), //信道估计两次fft输入完毕后拉高1clk
|
||
//MMSE信道估计结果RAM
|
||
.write_MMSE_wea (write_MMSE_wea),
|
||
.addrin_MMSE (addrin_MMSE),
|
||
.din_MMSE (din_MMSE),
|
||
//debug,溢出标志
|
||
.flagoverflow_fftpilot_26to14 (flagoverflow_fftpilot_26to14), //第1个fft结果截位，即导频fft结果的截位，26截到14
|
||
.flagoverflow_ChnZF_26to18 (flagoverflow_ChnZF_26to18), //第2个fft结果截位，即ZF信道估计结果的截位，26截到18
|
||
.flagoverflow_comdiv_34to20i (flagoverflow_comdiv_34to20i), //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到20
|
||
.flagoverflow_comdiv_34to20q (flagoverflow_comdiv_34to20q), //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到20
|
||
.flagoverflow_ifftzero_29to17i (flagoverflow_ifftzero_29to17i), //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
|
||
.flagoverflow_ifftzero_29to17q (flagoverflow_ifftzero_29to17q), //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
|
||
.flagoverflow_MMSEdiv_divisor_31to28(flagoverflow_MMSEdiv_divisor_31to28), //第2个除法器，即MMSE除法的分母截位，31截到28
|
||
.flagoverflow_divmmse_34to11 (flagoverflow_divmmse_34to11) //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11
|
||
);
|
||
|
||
//------------------------------------------------------------均衡模块-------------------------------------------------------//
|
||
|
||
data_equalizer data_equalizer_djy (
|
||
.clk (clk),
|
||
.rst (rst),
|
||
.EQUenable_vio (EQUenable_vio),
|
||
//进程flag
|
||
.nd_pilot2 (nd_pilot2),
|
||
.flag_ChnEstFFT_done (flag_ChnEstFFT_done), //信道估计两次fft输入完毕后拉高1clk(Chn_Estimate给出)
|
||
//数据的fifo，4个
|
||
.dout_data1i (dout_data1i),
|
||
.dout_data1q (dout_data1q),
|
||
.rd_en_data1 (rd_en_data1),
|
||
.dout_data2i (dout_data2i),
|
||
.dout_data2q (dout_data2q),
|
||
.rd_en_data2 (rd_en_data2),
|
||
.flag_dataow (flag_dataow), //拉高1clk，说明一段数据ow存储完毕，后端可开始连续读取
|
||
//fft核
|
||
.fft_out_i (fft_out_i),
|
||
.fft_out_q (fft_out_q),
|
||
.fft_out_nd (fft_out_nd),
|
||
.fft_index (fft_index),
|
||
.fft_in_i (fft_in_i_data),
|
||
.fft_in_q (fft_in_q_data),
|
||
.fft_in_nd (nd_datafft),
|
||
//ifft核
|
||
.ifft_out_i (ifft_out_i),
|
||
.ifft_out_q (ifft_out_q),
|
||
.ifft_out_nd (ifft_out_nd),
|
||
.ifft_index (ifft_index),
|
||
.ifft_in_i (ifft_in_i_data),
|
||
.ifft_in_q (ifft_in_q_data),
|
||
.ifft_in_nd (nd_dataifft),
|
||
//MMSE信道估计结果RAM
|
||
.addrout_MMSE (addrout_MMSE),
|
||
.dout_MMSE (dout_MMSE),
|
||
//均衡结果输出
|
||
.nd_SC_FDE_dout (nd_SC_FDE_dout),
|
||
.SC_FDE_douti (SC_FDE_douti),
|
||
.SC_FDE_doutq (SC_FDE_doutq),
|
||
//debug,溢出标志
|
||
.flagoverflow_ifftindata_28to20i (flagoverflow_ifftindata_28to20i), //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
|
||
.flagoverflow_ifftindata_28to20q (flagoverflow_ifftindata_28to20q), //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
|
||
.flagoverflow_fftdata_26to16i (flagoverflow_fftdata_26to16i), //数据段ow的fft输出截位，26截到16
|
||
.flagoverflow_fftdata_26to16q (flagoverflow_fftdata_26to16q), //数据段ow的fft输出截位，26截到16
|
||
.flagoverflow_FDE_dataout_29to10i(flagoverflow_FDE_dataout_29to10i), //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
|
||
.flagoverflow_FDE_dataout_29to10q(flagoverflow_FDE_dataout_29to10q) //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
|
||
);
|
||
|
||
endmodule
|