473 lines
12 KiB
Verilog
473 lines
12 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/11/18 21:03:55
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// Design Name:
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// Module Name: TSync_Abs_new4
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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//4倍过采样不内插
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//帧内不更新
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module TSync_Abs_new4(
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input clk,
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input rst,
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input framesync_Interpolation,
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output reg framesync_out4 = 1'd0,
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input [9:0] dataini,
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input [9:0] datainq,
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output reg TSyncout_nd = 1'd0,
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output reg [9:0] TSyncout_i = 10'd0,
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output reg [9:0] TSyncout_q = 10'd0,
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//debug
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output reg [1:0] cnt = 2'd0, //12.5
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output reg [1:0] flag_clk4 = 2'd0 //12.5
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);
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//-------------------------------------状态机控制----------------------------------------------//
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// reg [3:0] cnt = 4'd0;
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reg nd_1 = 1'd0;
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reg flag_framesync = 1'd0;
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// reg [3:0] flag_clk = 4'd0;
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// reg [1:0] flag_num = 2'd0;
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always @(posedge clk)begin
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if(rst)begin
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cnt <= 2'd3;
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nd_1 <= 1'd0;
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TSyncout_nd <= 1'd0;
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TSyncout_i <= 10'd0;
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TSyncout_q <= 10'd0;
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flag_framesync <= 1'd0;
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framesync_out4 <= 1'd0;
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end
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else begin
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cnt <= cnt + 2'd1;
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if(cnt == 2'd3) nd_1 <= 1'd1;
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else nd_1 <= 1'd0;
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if(framesync_Interpolation) begin
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if(cnt == flag_clk4) begin
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framesync_out4 <= 1'd1;
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TSyncout_nd <= 1'd1;
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TSyncout_i <= dataini;
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TSyncout_q <= datainq;
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flag_framesync <= 1'd0;
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end
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else begin
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framesync_out4 <= 1'd0;
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TSyncout_nd <= 1'd0;
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TSyncout_i <= 10'd0;
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TSyncout_q <= 10'd0;
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flag_framesync <= 1'd1;
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end
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end
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else begin
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framesync_out4 <= 1'd0;
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flag_framesync <= 1'd0;
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TSyncout_nd <= 1'd0;
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TSyncout_i <= 10'd0;
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TSyncout_q <= 10'd0;
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end
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// if(cnt == flag_clk4) begin
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// TSyncout_nd <= 1'd1;
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// TSyncout_i <= dataini;
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// TSyncout_q <= datainq;
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// end
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// else begin
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// TSyncout_nd <= 1'd0;
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// end
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end
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end
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//---------------------------------------求近似模值Abs，delay=6-------------------------------------//
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wire [10:0] data_Abs;
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ApproxAbs_v2 ApproxAbs_v2_tsync (
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.clk (clk),
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.ND (1'd1),
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.Din_I (dataini),
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.Din_Q (datainq),
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.Dout (data_Abs),
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.Rdy ()
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);
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reg nd_2 = 1'd0;
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reg nd_3 = 1'd0;
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reg nd_4 = 1'd0;
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reg nd_5 = 1'd0;
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reg nd_6 = 1'd0;
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reg nd_7 = 1'd0;
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always @(posedge clk)begin
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nd_2 <= nd_1;
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nd_3 <= nd_2;
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nd_4 <= nd_3;
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nd_5 <= nd_4;
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nd_6 <= nd_5;
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nd_7 <= nd_6;
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end
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//-------------------------------------累加，delay=1-------------------------------------------------//
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reg [19:0] acc_01 = 20'd0;
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reg [19:0] acc_02 = 20'd0;
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reg [19:0] acc_03 = 20'd0;
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reg [19:0] acc_04 = 20'd0;
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reg [1:0] cnt_4 =2'd0;
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reg nd_acc = 1'd0;
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reg nd_flag = 1'd0;
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reg flag_cnt_0 = 1'd0;
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reg [5:0] cnt_64 = 6'd0;
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reg [6:0] cnt_128 = 7'd0;
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reg [7:0] cnt_256 = 8'd0;
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reg [8:0] cnt_512 = 9'd0;
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reg [9:0] cnt_1024 = 10'd0;
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reg [2:0] state_tsync4 = 3'd0;
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always @(posedge clk)begin
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if(rst)begin
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acc_01 <= 20'd0;
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acc_02 <= 20'd0;
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acc_03 <= 20'd0;
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acc_04 <= 20'd0;
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cnt_4 <= 2'd3;
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nd_acc <= 1'd0;
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nd_flag<= 1'd0;
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cnt_64 <= 6'd0;
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cnt_128 <= 7'd0;
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cnt_256 <= 8'd0;
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cnt_512 <= 9'd0;
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cnt_1024 <= 10'd0;
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flag_cnt_0 <= 1'd0;
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state_tsync4 <= 3'd0;
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end
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else begin
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if(nd_6) cnt_4 <= 4'd0;
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else cnt_4 <= cnt_4 + 4'd1;
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if (nd_6) nd_flag <= 1'd1;
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else nd_flag <= nd_flag;
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case(state_tsync4)
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//等待第一次的数据幅值估计结果（与nd_7对齐）
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3'd0:begin
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if(nd_6) state_tsync4 <= 3'd1;
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else state_tsync4 <= state_tsync4;
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end
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//此clk内nd_7、第一次的数据幅值估计结果同时到来，cnt_4结果为4'd0。
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//累积，直到最后一个累积结束后转至下一状态
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3'd1:begin
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if(cnt_4==2'd3) begin
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cnt_64 <=cnt_64 +6'd1;
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cnt_128 <=cnt_128 +7'd1;
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cnt_256 <=cnt_256 +8'd1;
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cnt_512 <=cnt_512 +9'd1;
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cnt_1024 <=cnt_1024 +10'd1;
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if(cnt_512==9'd511) flag_cnt_0 <= 1'd1;
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else flag_cnt_0 <= 1'd0;
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end
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else begin
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cnt_64 <= cnt_64;
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cnt_128 <= cnt_128 ;
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cnt_256 <= cnt_256 ;
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cnt_512 <= cnt_512 ;
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cnt_1024 <= cnt_1024;
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flag_cnt_0 <= 1'd0;
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end
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if(cnt_512==9'd0) begin
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case(cnt_4)
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2'd0:begin
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acc_01 <= {9'd0,data_Abs};
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nd_acc <= 1'd0;
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end
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2'd1:begin
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acc_02 <= {9'd0,data_Abs};
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nd_acc <= 1'd0;
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end
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2'd2:begin
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acc_03 <= {9'd0,data_Abs};
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nd_acc <= 1'd0;
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end
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2'd3:begin
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acc_04 <= {9'd0,data_Abs};
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nd_acc <= 1'd1;
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end
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endcase
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end
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else begin
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case(cnt_4)
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2'd0:begin
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acc_01 <= acc_01 + {9'd0,data_Abs};
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nd_acc <= 1'd0;
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end
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2'd1:begin
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acc_02 <= acc_02 + {9'd0,data_Abs};
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nd_acc <= 1'd0;
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end
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2'd2:begin
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acc_03 <= acc_03 + {9'd0,data_Abs};
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nd_acc <= 1'd0;
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end
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2'd3:begin
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acc_04 <= acc_04 + {9'd0,data_Abs};
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nd_acc <= 1'd1;
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end
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endcase
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end
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if(cnt_512==9'd511&&cnt_4==2'd3) state_tsync4 <= 3'd2;
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else state_tsync4 <= state_tsync4;
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end
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3'd2:begin
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state_tsync4 <= state_tsync4;
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flag_cnt_0 <= 1'd0;
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end
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default:state_tsync4 <= 3'd0;
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endcase
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end
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end
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//---------------------------------------排序找最大值，delay=3-------------------------------------------------//
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reg [19:0] temp_1_01 = 20'd0;
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reg [19:0] temp_1_02 = 20'd0;
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reg [1:0] flag_clk_1_01 =2'd0;
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reg [1:0] flag_clk_1_02 =2'd0;
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reg nd_acc1 = 1'd0;
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//ila用
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reg [19:0] acc_01_reg = 20'd0;
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reg [19:0] acc_02_reg = 20'd0;
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reg [19:0] acc_03_reg = 20'd0;
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reg [19:0] acc_04_reg = 20'd0;
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always @(posedge clk)begin
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if(rst)begin
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temp_1_01 <= 20'd0;
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temp_1_02 <= 20'd0;
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flag_clk_1_01 <=2'd0;
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flag_clk_1_02 <=2'd0;
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nd_acc1 <= 1'd0;
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//ila用
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acc_01_reg <= 20'd0;
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acc_02_reg <= 20'd0;
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acc_03_reg <= 20'd0;
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acc_04_reg <= 20'd0;
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end
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else begin
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if(nd_acc&&flag_cnt_0) begin
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nd_acc1 <= 1'd1;
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//ila用
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acc_01_reg <= acc_01;
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acc_02_reg <= acc_02;
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acc_03_reg <= acc_03;
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acc_04_reg <= acc_04;
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//ila用
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if(acc_01>=acc_02) begin
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temp_1_01 <= acc_01;
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flag_clk_1_01 <= 2'd0;
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end
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else begin
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temp_1_01 <= acc_02;
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flag_clk_1_01 <= 2'd1;
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end
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if(acc_03>=acc_04) begin
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temp_1_02 <= acc_03;
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flag_clk_1_02 <= 2'd2;
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end
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else begin
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temp_1_02 <= acc_04;
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flag_clk_1_02 <= 2'd3;
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end
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end
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else nd_acc1 <= 1'd0;
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end
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end
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//----------------------------------------------------给采样标志,delay=1--------------------------------------//
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reg nd_acc2 = 1'd0;
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always @(posedge clk)begin
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if(rst)begin
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flag_clk4 <= 2'd0;
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nd_acc2 <= 1'd0;
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end
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else begin
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nd_acc2 <= nd_acc1;
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if(nd_acc1) begin
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if(temp_1_01>=temp_1_02) begin
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flag_clk4 <= flag_clk_1_01;
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end
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else begin
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flag_clk4 <= flag_clk_1_02;
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end
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end
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end
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end
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//ila用
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// reg [6:0] state_check = 7'd0;
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// always @(posedge clk)begin
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// if(rst)begin
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// state_check <= 7'd0;
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// flag_TSync_check<= 1'd0;
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// cnt_tsync_shixu <= 4'd0;
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// flag_tongdao <= 1'd0;
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// acc_tsync <= 20'd0;
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// num_tsync <= num_tsync;
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// end
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// else begin
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// case(state_check)
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// 7'd0:begin
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// if(nd_acc4) begin
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// flag_TSync_check<= 1'd0;
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// state_check <= 7'd1;
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// end
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// else begin
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// flag_TSync_check<= 1'd0;
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// state_check <= state_check;
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// end
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// cnt_tsync_shixu <= 4'd0;
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// flag_tongdao <= 1'd0;
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// acc_tsync <= acc_tsync;
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// num_tsync <= num_tsync;
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// end
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// 7'd1:begin
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// if(flag_save) begin
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// flag_TSync_check<= 1'd0;
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// state_check <= 7'd2;
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// end
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// else begin
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// flag_TSync_check<= 1'd0;
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// state_check <= state_check;
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// end
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// cnt_tsync_shixu <= 4'd1 + cnt_tsync_shixu;
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// flag_tongdao <= 1'd0;
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// acc_tsync <= acc_tsync;
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// num_tsync <= num_tsync;
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// end
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// 7'd2:begin
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// if(cnt==2'd3) begin
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// flag_TSync_check<= 1'd1;
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// state_check <= 7'd3;
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// end
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// else begin
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// flag_TSync_check<= 1'd0;
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// state_check <= state_check;
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// end
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// cnt_tsync_shixu <= 4'd1 + cnt_tsync_shixu;
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// flag_tongdao <= 1'd0;
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// acc_tsync <= acc_tsync;
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// num_tsync <= num_tsync;
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// end
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// 7'd03:begin acc_tsync <= acc_01_reg; num_tsync <= 6'd00; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd04; end
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// 7'd04:begin acc_tsync <= acc_02_reg; num_tsync <= 6'd01; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd05; end
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// 7'd05:begin acc_tsync <= acc_03_reg; num_tsync <= 6'd02; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd06; end
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// 7'd06:begin acc_tsync <= acc_04_reg; num_tsync <= 6'd03; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd07; end
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// 7'd07:begin acc_tsync <= acc_05_reg; num_tsync <= 6'd04; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd08; end
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// 7'd08:begin acc_tsync <= acc_06_reg; num_tsync <= 6'd05; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd09; end
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// 7'd09:begin acc_tsync <= acc_07_reg; num_tsync <= 6'd06; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd10; end
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// 7'd10:begin acc_tsync <= acc_08_reg; num_tsync <= 6'd07; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd11; end
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// 7'd11:begin acc_tsync <= acc_09_reg; num_tsync <= 6'd08; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd12; end
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// 7'd12:begin acc_tsync <= acc_10_reg; num_tsync <= 6'd09; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd13; end
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// 7'd13:begin acc_tsync <= acc_11_reg; num_tsync <= 6'd10; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd14; end
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// 7'd14:begin acc_tsync <= acc_12_reg; num_tsync <= 6'd11; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd15; end
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// 7'd15:begin acc_tsync <= acc_13_reg; num_tsync <= 6'd12; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd16; end
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// 7'd16:begin acc_tsync <= acc_14_reg; num_tsync <= 6'd13; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd17; end
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// 7'd17:begin acc_tsync <= acc_15_reg; num_tsync <= 6'd14; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd18; end
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// 7'd18:begin acc_tsync <= acc_16_reg; num_tsync <= 6'd15; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd0; end
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// endcase
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// end
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// end
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// integer handle01;
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// integer handle02;
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// reg enable = 0;
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// initial begin
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// handle01=$fopen("TSyncout_i.txt","w"); $fclose(handle01);
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// handle02=$fopen("TSyncout_q.txt","w"); $fclose(handle02);
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// #10;
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// enable = 1;
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// end
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// always@(posedge clk)begin
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// if(enable)begin
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// if(TSyncout_nd)begin
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// handle01=$fopen("TSyncout_i.txt","a+");$fwrite(handle01,"%d\n",$signed(TSyncout_i));$fclose(handle01);
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// handle02=$fopen("TSyncout_q.txt","a+");$fwrite(handle02,"%d\n",$signed(TSyncout_q));$fclose(handle02);
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// end
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// end
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// end
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endmodule
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