52 lines
1.3 KiB
Verilog
52 lines
1.3 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 21:36:07 01/20/2018
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// Design Name:
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// Module Name: abs_min_4din
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module abs_min_4din #(
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parameter WIDTH = 4'd8
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) (
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input clk,
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input [WIDTH-1:0] din01, //din01<din02
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input [WIDTH-1:0] din02,
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input [WIDTH-1:0] din03, //din03<din04
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input [WIDTH-1:0] din04,
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output reg [WIDTH-1:0] dout_min = 8'd0,
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output reg [WIDTH-1:0] dout_sec = 8'd0
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); //输出相对输入延时1个周期
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always @(posedge clk) begin
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if (din02 <= din03) begin
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dout_min <= din01;
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dout_sec <= din02;
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end
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else begin
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if (din01 <= din03) begin
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dout_min <= din01;
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dout_sec <= din03;
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end
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else begin
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dout_min <= din03;
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dout_sec <= (din01 < din04) ? din01 : din04;
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end
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end
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end
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endmodule
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