53 lines
1.3 KiB
Verilog
53 lines
1.3 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2023/11/14 16:20:11
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// Design Name:
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// Module Name: ad9361_spi_interface
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module ad9361_spi_interface (
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input ad9361_spi_miso,
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output ad9361_spi_csn,
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output ad9361_spi_clk,
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output ad9361_spi_mosi,
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// spi interface
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input spi_sclk,
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input [1:0] spi_cs,
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output reg spi_sdi,
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input spi_sdo,
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input spi_sdo_t,
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input spi_three_wire,
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input spi_active
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);
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// ad9361 - three-wire spi or four-wire spi
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assign ad9361_spi_clk = spi_sclk;
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assign ad9361_spi_csn = spi_cs[1];
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assign ad9361_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
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// select sdi signal
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always @(*) begin
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if (~ad9361_spi_csn) spi_sdi = spi_three_wire ? ad9361_spi_mosi : ad9361_spi_miso;
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else spi_sdi = 1'bz;
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end
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endmodule
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