159 lines
3.4 KiB
Verilog
159 lines
3.4 KiB
Verilog
`timescale 1ns / 1ns
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module add_prefix #(
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//! if the WIDTH or DATA_LEN parameter is changed, make sure the shift IP inside is also changed
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parameter WIDTH = 2,
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parameter DATA_LEN = 256,
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parameter PREFIX_LEN = 32
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) (
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input clk,
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input start,
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output reg ready,
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input [WIDTH-1:0] data_in,
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output reg data_in_ready,
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output reg [WIDTH-1:0] data_out,
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output reg data_out_valid
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);
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localparam CNT_WIDTH = $clog2(DATA_LEN);
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// ******** Wire & Reg ********
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wire [ WIDTH-1:0] shift_out;
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reg [CNT_WIDTH : 0] cnt_in;
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reg [ CNT_WIDTH:0] cnt_out;
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reg [ 2:0] cs = 0;
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reg [ 2:0] ns = 0;
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localparam [2:0] S_IDLE = 0;
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localparam [2:0] S_IN = 1;
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localparam [2:0] S_OUT = 2;
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// ******** Assingment ********
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// ******** Logic Block ********
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always @(posedge clk) begin
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cs <= ns;
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end
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always @(*) begin
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case (cs)
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S_IDLE: begin
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if (start) begin
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ns = S_IN;
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end
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else begin
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ns = S_IDLE;
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end
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end
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S_IN: begin
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if (cnt_in == DATA_LEN - PREFIX_LEN - 1) begin
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ns = S_OUT;
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end
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else begin
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ns = S_IN;
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end
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end
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S_OUT: begin
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if (cnt_out == DATA_LEN + PREFIX_LEN - 1) begin
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ns = S_IDLE;
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end
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else begin
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ns = S_OUT;
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end
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end
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default: begin
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ns = S_IDLE;
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end
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endcase
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end
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// module ready to receive new packet
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always @(posedge clk) begin
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if (cs == S_IDLE && ~start) begin
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ready <= 1'b1;
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end
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else begin
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ready <= 1'b0;
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end
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end
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// counts the data in
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always @(posedge clk) begin
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if (cs == S_IN || cnt_in < DATA_LEN - 1 && cnt_in > 0) begin
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cnt_in <= cnt_in + 1;
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end
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else begin
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cnt_in <= 0;
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end
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end
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always @(posedge clk) begin
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if (start) begin
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data_in_ready <= 1'b1;
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end
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else if (cnt_in == DATA_LEN - 1 || cs == S_IDLE) begin
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data_in_ready <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if (cs == S_OUT) begin
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cnt_out <= cnt_out + 1;
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end
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else begin
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cnt_out <= 0;
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end
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end
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always @(posedge clk) begin
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if (cs == S_OUT) begin
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if (cnt_out < PREFIX_LEN) begin
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data_out <= data_in;
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end
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else begin
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data_out <= shift_out;
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end
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end
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else begin
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data_out <= 0;
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end
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end
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always @(posedge clk) begin
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if (cs == S_OUT) begin
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data_out_valid <= 1'b1;
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end
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else begin
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data_out_valid <= 1'b0;
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end
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end
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// ******** Inst ********
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shift256_8 u_shift256_8 (
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.CLK(clk), // input wire CLK
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.D (data_in), // input wire [31 : 0] D
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.Q (shift_out) // output wire [31 : 0] Q
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);
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// ******** Debug ********
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endmodule
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