262 lines
10 KiB
Verilog
262 lines
10 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2020/12/14 14:44:05
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// Design Name:
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// Module Name: phase_adjust
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module phase_adjust (
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input clk,
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input rst,
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input [9:0] din_i,
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input [9:0] din_q,
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input nd,
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input framesync,
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output reg rdy,
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output [9:0] dout_i,
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output [9:0] dout_q
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);
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reg [ 7:0] addra = 8'd0;
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reg [19:0] dina = 20'd0;
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reg [ 7:0] addrb = 8'd0;
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wire [19:0] doutb;
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RAM_phase RAM_phase (
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.clka (clk), // input clka
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.wea (1'b1), // input [0 : 0] wea
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.addra(addra), // input [9 : 0] addra
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.dina (dina), // input [15 : 0] dina
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.clkb (clk), // input clkb
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.addrb(addrb), // input [10 : 0] addrb
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.doutb(doutb) // output [7 : 0] doutb
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);
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wire [10:0] squarei;
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wire [10:0] squareq;
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wire [47:0] m_axis_dout_tdata;
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wire m_axis_dout_tvalid;
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CompMultIP CompMultIP1 (
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.aclk (clk), // input wire aclk
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.s_axis_a_tvalid (nd), // input wire s_axis_a_tvalid
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.s_axis_a_tdata ({6'd0, din_q, 6'd0, din_i}), // input wire [31 : 0] s_axis_a_tdata
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.s_axis_b_tvalid (nd), // input wire s_axis_b_tvalid
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.s_axis_b_tdata ({6'd0, din_q, 6'd0, din_i}), // input wire [31 : 0] s_axis_b_tdata
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.m_axis_dout_tvalid(m_axis_dout_tvalid), // output wire m_axis_dout_tvalid
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.m_axis_dout_tdata (m_axis_dout_tdata) // output wire [47 : 0] m_axis_dout_tdata
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);
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assign squareq = m_axis_dout_tdata[40:30];
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assign squarei = m_axis_dout_tdata[16:6];
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wire [11:0] square2i;
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wire [11:0] square2q;
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wire [47:0] m_axis_dout_tdata2;
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wire m_axis_dout_tvalid2;
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CompMultIP2 CompMultIP2 (
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.aclk (clk), // input wire aclk
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.s_axis_a_tvalid (m_axis_dout_tvalid), // input wire s_axis_a_tvalid
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.s_axis_a_tdata ({5'd0, squareq, 5'd0, squarei}), // input wire [31 : 0] s_axis_a_tdata
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.s_axis_b_tvalid (m_axis_dout_tvalid), // input wire s_axis_b_tvalid
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.s_axis_b_tdata ({5'd0, squareq, 5'd0, squarei}), // input wire [31 : 0] s_axis_b_tdata
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.m_axis_dout_tvalid(m_axis_dout_tvalid2), // output wire m_axis_dout_tvalid
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.m_axis_dout_tdata (m_axis_dout_tdata2) // output wire [47 : 0] m_axis_dout_tdata
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);
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assign square2q = m_axis_dout_tdata2[41:30];
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assign square2i = m_axis_dout_tdata2[17:6];
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reg [19:0] sum256i = 20'd0;
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reg [19:0] sum256q = 20'd0;
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reg [ 9:0] addradelay = 10'd0;
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reg [ 3:0] state_phase;
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reg [ 9:0] cnt_phase;
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reg sum_rdy;
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reg rotate_nd;
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reg [ 9:0] phase_estm;
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reg [ 9:0] phase_shengyu;
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reg [ 9:0] phase_final;
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reg [ 9:0] phase_pi = 10'b0110010010;
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wire [ 9:0] phase_out;
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wire [ 5:0] phase_out_head;
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wire phaserdy;
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atan2_phase atan2_phase (
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.aclk (clk), // input wire aclk
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.s_axis_cartesian_tvalid(sum_rdy), // input wire s_axis_cartesian_tvalid
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.s_axis_cartesian_tdata ({4'd0, sum256q, 4'd0, sum256i}), // input wire [47 : 0] s_axis_cartesian_tdata
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.m_axis_dout_tvalid (phaserdy), // output wire m_axis_dout_tvalid
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.m_axis_dout_tdata ({phase_out_head, phase_out}) // output wire [15 : 0] m_axis_dout_tdata
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);
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wire [5:0] rotate_headq;
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wire [5:0] rotate_headi;
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wire rotate_rdy;
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atan2_rotate atan2_rotate (
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.aclk (clk), // input wire aclk
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.s_axis_cartesian_tvalid(rotate_nd), // input wire s_axis_cartesian_tvalid
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.s_axis_cartesian_tdata ({6'd0, doutb[19:10], 6'd0, doutb[9:0]}), // input wire [47 : 0] s_axis_cartesian_tdata
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.s_axis_phase_tvalid (rotate_nd), // input wire s_axis_cartesian_tvalid
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.s_axis_phase_tdata ({6'd0, phase_final[9], phase_final[9], phase_final[9:2]}), // input wire [47 : 0] s_axis_cartesian_tdata
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.m_axis_dout_tvalid (rotate_rdy), // output wire m_axis_dout_tvalid
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.m_axis_dout_tdata ({rotate_headq, dout_q, rotate_headi, dout_i}) // output wire [15 : 0] m_axis_dout_tdata
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);
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always @(posedge clk) begin
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if (rst) begin
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state_phase <= 4'd0;
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addradelay <= 10'd0;
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sum256i <= 20'd0;
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sum256q <= 20'd0;
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cnt_phase <= 10'd0;
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sum_rdy <= 1'b0;
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phase_estm <= 10'd0;
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phase_shengyu <= 10'd0;
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phase_final <= 10'd0;
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rotate_nd <= 1'b0;
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rdy <= 1'b0;
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end
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else begin
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rdy <= rotate_rdy;
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case (state_phase)
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4'd0: begin
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if (framesync) begin
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state_phase <= 4'd1;
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end
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else begin
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state_phase <= 4'd0;
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end
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end
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4'd1: begin
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if (nd) begin
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addradelay <= addradelay + 10'd1;
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dina <= {din_q, din_i};
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addra <= addradelay[7:0];
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if (addradelay == 10'd255) begin
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state_phase <= 4'd2;
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addradelay <= 10'd0;
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end
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else begin
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state_phase <= 4'd1;
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end
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end
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else begin
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state_phase <= 4'd1;
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addradelay <= addradelay;
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addra <= addra;
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dina <= dina;
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state_phase <= 2'd1;
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end
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if (m_axis_dout_tvalid2) begin
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cnt_phase <= cnt_phase + 10'd1;
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sum256i <= sum256i + {square2i[11], square2i[11], square2i[11], square2i[11], square2i[11], square2i[11], square2i[11], square2i[11], square2i};
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sum256q <= sum256q + {square2q[11], square2q[11], square2q[11], square2q[11], square2q[11], square2q[11], square2q[11], square2q[11], square2q};
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end
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else begin
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cnt_phase <= cnt_phase;
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sum256i <= sum256i;
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sum256q <= sum256q;
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end
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end
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4'd2: begin
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if (m_axis_dout_tvalid2) begin
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if (cnt_phase == 10'd255) begin
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cnt_phase <= 10'd0;
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state_phase <= 4'd3;
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sum_rdy <= 1'b1;
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end
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else begin
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cnt_phase <= cnt_phase + 10'd1;
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sum_rdy <= 1'b0;
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state_phase <= 4'd2;
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end
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sum256i <= sum256i + {square2i[11], square2i[11], square2i[11], square2i[11], square2i[11], square2i[11], square2i[11], square2i[11], square2i};
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sum256q <= sum256q + {square2q[11], square2q[11], square2q[11], square2q[11], square2q[11], square2q[11], square2q[11], square2q[11], square2q};
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end
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else begin
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cnt_phase <= cnt_phase;
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state_phase <= 4'd2;
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sum256i <= sum256i;
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sum256q <= sum256q;
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end
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end
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4'd3: begin
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sum_rdy <= 1'b0;
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if (phaserdy) begin
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sum256i <= 20'd0;
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sum256q <= 20'd0;
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phase_estm <= phase_out;
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if (phase_out[9]) begin
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phase_shengyu <= phase_pi + phase_out;
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end
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else begin
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phase_shengyu <= phase_pi - phase_out;
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end
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state_phase <= 4'd4;
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end
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else begin
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phase_estm <= phase_estm;
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state_phase <= 4'd3;
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end
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end
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4'd4: begin
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if (phase_estm[9]) begin
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phase_final <= -phase_shengyu;
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end
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else begin
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phase_final <= phase_shengyu;
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end
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if (cnt_phase == 10'd0) begin
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cnt_phase <= cnt_phase + 10'd1;
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addrb <= 10'd0;
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rotate_nd <= 1'b1;
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end
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else if (cnt_phase == 10'd256) begin
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cnt_phase <= 10'd0;
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rotate_nd <= 1'b0;
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state_phase <= 4'd1;
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addrb <= 8'd0;
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end
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else begin
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cnt_phase <= cnt_phase + 10'd1;
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addrb <= addrb + 8'd1;
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rotate_nd <= 1'b1;
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end
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end
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default: begin
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if (framesync) begin
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state_phase <= 4'd1;
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end
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else begin
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state_phase <= 4'd0;
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end
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end
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endcase
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end
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end
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endmodule
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