313 lines
10 KiB
Verilog
313 lines
10 KiB
Verilog
// * Engineer:
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// * *************************************************** *
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// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
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// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║ ██║ *
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// * ███╔╝ ██║ ██║██████╔╝██║ ██║██║ ███╗███████║ *
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// * ███╔╝ ██║ ██║██╔══██╗██║ ██║██║ ██║██╔══██║ *
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// * ███████╗╚██████╔╝██║ ██║╚██████╔╝╚██████╔╝██║ ██║ *
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// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
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// * *************************************************** *
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// * Update Date: 2024/7/16
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// * NOTE : this file use the sign bit number to estimate the
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// * NOTE : signal power, the drawback of this module is that
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// * NOTE : little amplitude over the threhold will be treated
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// * NOTE : as overflow, thus indicating a flag_too_high pulse
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// * NOTE :
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// * NOTE : as improvemnt, we can use a number as the threshold
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// * NOTE : such as 1800 ( under the 12bit input ).
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// * NOTE :
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module power_measure (
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input clk,
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input rst,
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input start,
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// data input
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input wire [11:0] data_i,
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input wire [11:0] data_q,
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output reg flag_too_high,
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output reg flag_too_low,
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output reg power_measure_done_pulse
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);
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localparam CNT_WAIT_9361_MAX = 80; //* 等待周期数
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localparam CNT_MEASURING_MAX = 256; // * 观察64个周期
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localparam CNT_ADJUST_TIMES_MAX = 25;
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localparam CNT_AMP_TOO_HIGH_THRESHOLD = 6;
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// ******** Wire & Reg ********
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// * NOTE: during measuring, the sign bit numbers changes .
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// * NOTE: as the signal amplitude(power) changes.
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// * NOTE: thus, measuring the sign bit numbers can indicate
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// * NOTE: the power of the signal.
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// * NOTE:
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// * NOTE: the sign bit number min, represents the minimum of
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// * NOTE: the sign bit number, meaning the highest signal power.
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// * NOTE: if sign_bit_num_min_* is too small (1 or 2), we should
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// * NOTE: decrease the input signal power.
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// * NOTE:
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// * NOTE: reversely, the sign_bit_num_max_* means the maximum of
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// * NOTE: the amplitude, if signal power is too small, it will be
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// * NOTE: small, indicating increasing the input signal power.
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// * NOTE:
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// * NOTE: for a modulated signal, the power can not be indicated by
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// * NOTE: max sign bit number, so we should only control the min sign
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// * NOTE: bit numer.
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reg [ 3:0] sign_bit_num_i;
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reg [ 3:0] sign_bit_num_min_i;
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reg [ 3:0] sign_bit_num_q;
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reg [ 3:0] sign_bit_num_min_q;
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// startup
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reg [ 7:0] cnt_startup; // set rx gain to max each time start posedge comes
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reg [ 3:0] cnt_amp_too_high; // for short cuirt
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// abs
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reg [11:0] data_i_abs;
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reg [11:0] data_q_abs;
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// measuring the signal power
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reg [15:0] cnt_measuring;
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// for waiting ad9361 adjust done
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reg [15:0] cnt_wait_9361;
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// the times fsm have adjust already
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reg [ 7:0] cnt_adjust_times;
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// fsm var
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localparam S_MEASURE_IDLE = 0;
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localparam S_MEASURE_ING = 1;
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localparam S_MEASURE_DONE = 2;
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localparam S_MEASURE_ADJ = 3;
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localparam S_MEASURE_STARTUP = 4;
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reg [2:0] cs = S_MEASURE_IDLE;
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reg [2:0] ns = S_MEASURE_IDLE;
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// ******** Assingment ********
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// ******** Logic Block ********
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always @(posedge clk) begin
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if (rst || start) begin
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cnt_startup <= 0;
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end
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else if (cs == S_MEASURE_STARTUP && cnt_startup < 255) begin
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cnt_startup <= cnt_startup + 1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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cs <= S_MEASURE_IDLE;
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end
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else begin
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cs <= ns;
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end
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end
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// fsm
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always @(*) begin
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case (cs)
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S_MEASURE_IDLE: begin
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if (start) begin
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ns = S_MEASURE_STARTUP;
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end
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else begin
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ns = S_MEASURE_IDLE;
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end
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end
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S_MEASURE_STARTUP: begin
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if (cnt_startup == 255) begin
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ns = S_MEASURE_ING;
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end
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else begin
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ns = S_MEASURE_STARTUP;
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end
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end
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S_MEASURE_ING: begin
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if (cnt_measuring == CNT_MEASURING_MAX - 1 || cnt_amp_too_high == CNT_AMP_TOO_HIGH_THRESHOLD - 1) begin
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ns = S_MEASURE_DONE;
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end
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else begin
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ns = S_MEASURE_ING;
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end
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end
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S_MEASURE_DONE: begin
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ns = S_MEASURE_ADJ;
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end
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S_MEASURE_ADJ: begin
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// mgc adjust done
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if (cnt_adjust_times == CNT_ADJUST_TIMES_MAX - 1) begin
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ns = S_MEASURE_IDLE;
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end
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// wait ad9361 feedback
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else if (cnt_wait_9361 == CNT_WAIT_9361_MAX - 1) begin
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ns = S_MEASURE_ING;
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end
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else begin
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ns = S_MEASURE_ADJ;
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end
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end
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default: begin
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ns = S_MEASURE_IDLE;
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end
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endcase
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end
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always @(posedge clk) begin
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if (cs == S_MEASURE_ING) begin
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cnt_measuring <= cnt_measuring + 1;
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end
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else begin
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cnt_measuring <= 0;
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end
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end
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always @(posedge clk) begin
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if (cs == S_MEASURE_ADJ) begin
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cnt_wait_9361 <= cnt_wait_9361 + 1;
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end
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else begin
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cnt_wait_9361 <= 0;
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end
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end
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always @(posedge clk) begin
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if (cs == S_MEASURE_DONE) begin
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cnt_adjust_times <= cnt_adjust_times + 1;
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end
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else if (cs == S_MEASURE_IDLE) begin
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cnt_adjust_times <= 0;
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end
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end
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always @(posedge clk) begin
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if (cs == S_MEASURE_ING && (sign_bit_num_i == 1 || sign_bit_num_q == 1)) begin
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cnt_amp_too_high <= cnt_amp_too_high + 1;
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end
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else if (cs == S_MEASURE_ADJ || cs == S_MEASURE_IDLE) begin
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cnt_amp_too_high <= 0;
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end
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else begin
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cnt_amp_too_high <= cnt_amp_too_high;
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end
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end
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always @(posedge clk) begin
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if (cs == S_MEASURE_ADJ && ns == S_MEASURE_IDLE) begin
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power_measure_done_pulse <= 1;
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end
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else begin
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power_measure_done_pulse <= 0;
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end
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end
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// get the abs value
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always @(posedge clk) begin
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// i
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if (data_i[11]) begin
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data_i_abs <= -data_i;
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end
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else begin
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data_i_abs <= data_i;
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end
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// q
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if (data_q[11]) begin
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data_q_abs <= -data_q;
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end
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else begin
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data_q_abs <= data_q;
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end
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end
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// get the sign number bit number of the temporary 12 bit number
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always @(*) begin
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casez (data_i_abs)
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12'b1000_0000_0000: sign_bit_num_i <= 8'd1;
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12'b01??_????_????: sign_bit_num_i <= 8'd1;
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12'b001?_????_????: sign_bit_num_i <= 8'd2;
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12'b0001_????_????: sign_bit_num_i <= 8'd3;
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12'b0000_1???_????: sign_bit_num_i <= 8'd4;
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12'b0000_01??_????: sign_bit_num_i <= 8'd5;
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12'b0000_001?_????: sign_bit_num_i <= 8'd6;
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12'b0000_0001_????: sign_bit_num_i <= 8'd7;
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12'b0000_0000_1???: sign_bit_num_i <= 8'd8;
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12'b0000_0000_01??: sign_bit_num_i <= 8'd9;
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12'b0000_0000_001?: sign_bit_num_i <= 8'd10;
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12'b0000_0000_0001: sign_bit_num_i <= 8'd11;
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default: begin
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sign_bit_num_i <= 8'd12;
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end
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endcase
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end
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// get the sign number bit number of the temporary 12 bit number
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always @(*) begin
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casez (data_q_abs)
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12'b1000_0000_0000: sign_bit_num_q <= 8'd1;
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12'b01??_????_????: sign_bit_num_q <= 8'd1;
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12'b001?_????_????: sign_bit_num_q <= 8'd2;
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12'b0001_????_????: sign_bit_num_q <= 8'd3;
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12'b0000_1???_????: sign_bit_num_q <= 8'd4;
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12'b0000_01??_????: sign_bit_num_q <= 8'd5;
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12'b0000_001?_????: sign_bit_num_q <= 8'd6;
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12'b0000_0001_????: sign_bit_num_q <= 8'd7;
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12'b0000_0000_1???: sign_bit_num_q <= 8'd8;
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12'b0000_0000_01??: sign_bit_num_q <= 8'd9;
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12'b0000_0000_001?: sign_bit_num_q <= 8'd10;
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12'b0000_0000_0001: sign_bit_num_q <= 8'd11;
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default: begin
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sign_bit_num_q <= 8'd12;
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end
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endcase
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end
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always @(posedge clk) begin
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if (cs == S_MEASURE_IDLE || cs == S_MEASURE_ADJ) begin
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sign_bit_num_min_i <= 8'd11;
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sign_bit_num_min_q <= 8'd11;
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end
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else if (cs == S_MEASURE_ING) begin
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if (sign_bit_num_min_i > sign_bit_num_i) begin
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sign_bit_num_min_i <= sign_bit_num_i;
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end
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if (sign_bit_num_min_q > sign_bit_num_q) begin
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sign_bit_num_min_q <= sign_bit_num_q;
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end
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end
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end
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// * flag_too_* generate logic, the core of the module
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always @(posedge clk) begin
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if (cnt_startup[2:0] == 3'b101 && cnt_startup <= 200) begin
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flag_too_high <= 0;
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flag_too_low <= 1;
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end
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else if (cs == S_MEASURE_DONE) begin
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// * 若符号位太多，则信号太小，需要增加信号功率
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if (sign_bit_num_min_i >= 3 || sign_bit_num_min_q >= 3) begin
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flag_too_low <= 1;
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end
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// * 若符号位太少，则信号太大，需要降低信号功率
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else if (sign_bit_num_min_i <= 1 || sign_bit_num_min_q <= 1 || cnt_amp_too_high >= CNT_AMP_TOO_HIGH_THRESHOLD - 1) begin
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flag_too_high <= 1;
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end
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end
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else begin
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flag_too_high <= 0;
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flag_too_low <= 0;
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end
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end
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endmodule
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