94 lines
3.3 KiB
Verilog
94 lines
3.3 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2020/10/04 13:29:02
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// Design Name:
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// Module Name: shift_reg
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module shift_reg #(
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parameter DATA_WIDTH = 8,
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parameter DEPTH = 4
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) (
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input clk,
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(* max_fanout = 256 *) input rst,
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input we,
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input [DATA_WIDTH-1:0] din,
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output [DATA_WIDTH-1:0] dout
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);
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// generate
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// if (DEPTH > 1) begin
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// reg [DEPTH-1:0] shift_register[DATA_WIDTH-1:0];
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// genvar shift_bit_cnt;
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// for (shift_bit_cnt = 0; shift_bit_cnt < DATA_WIDTH; shift_bit_cnt = shift_bit_cnt + 1) begin : shift_each_bit
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// always @(posedge clk) begin
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// if (we) shift_register[shift_bit_cnt] <= {din[shift_bit_cnt], shift_register[shift_bit_cnt][DEPTH-1:1]};
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// else shift_register[shift_bit_cnt] <= shift_bit_cnt[shift_bit_cnt];
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// end
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// end
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// genvar output_bit_cnt;
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// for (output_bit_cnt = 0; output_bit_cnt < DATA_WIDTH; output_bit_cnt = output_bit_cnt + 1) begin : output_each_bit
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// assign dout[output_bit_cnt] = shift_register[output_bit_cnt][0];
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// end
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// end
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// else // just a reg
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// begin
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// reg [DATA_WIDTH-1:0] shift_register;
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// always @(posedge clk) begin
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// if (we) shift_register <= din;
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// else shift_register <= shift_register;
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// end
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// assign dout = shift_register;
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// end
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// endgenerate
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generate
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if (DEPTH > 1) begin
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reg [DATA_WIDTH-1:0] shift_register[DEPTH-1:0];
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genvar shift_reg_cnt;
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for (shift_reg_cnt = 0; shift_reg_cnt < DEPTH; shift_reg_cnt = shift_reg_cnt + 1) begin : shift_each_reg
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always @(posedge clk) begin
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if (rst) begin
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shift_register[shift_reg_cnt][DATA_WIDTH-1:0] <= 'd0;
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end
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else if (we) begin
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if (shift_reg_cnt == 0) begin
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shift_register[shift_reg_cnt] <= din;
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end
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else begin
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shift_register[shift_reg_cnt] <= shift_register[shift_reg_cnt-1];
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end
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end
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else shift_register[shift_reg_cnt] <= shift_register[shift_reg_cnt];
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end
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end
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assign dout = shift_register[DEPTH-1];
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end
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else // just a reg
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begin
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reg [DATA_WIDTH-1:0] shift_register;
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always @(posedge clk) begin
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if (we) shift_register <= din;
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else shift_register <= shift_register;
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end
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assign dout = shift_register;
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end
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endgenerate
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endmodule
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