76 lines
1.5 KiB
Verilog
76 lines
1.5 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/08/03 14:53:56
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// Design Name:
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// Module Name: trunc_25to12_2dly
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module trunc_25to12_2dly(
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clk,
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din_nd,
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din,
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ctrl,
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dout_nd,
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dout,
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ovrflw
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);
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//--------------------- IN/OUT ------------------------
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input clk;
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input din_nd;
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input [24:0] din;
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input ctrl;
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output reg dout_nd = 0;
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output reg [11:0] dout = 0;
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output reg ovrflw = 0;
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//---------------------- delay -----------------------
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reg [24:0] din_dly = 0;
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always @(posedge clk)
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din_dly <= din;
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reg sign_bit = 0;
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always @(posedge clk)
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sign_bit <= din[24];
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//---------------------- flag -------------------------
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reg signbit3 = 0;
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always @(posedge clk)
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if(din[24:22] == 3'b000 || din[24:22] == 3'b111)
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signbit3 <= 1'b1;
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else
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signbit3 <= 1'b0;
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//------------------------------------------------------
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always @(posedge clk)
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if(signbit3 == 1'b1)
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begin
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dout <= din_dly[22:11];
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ovrflw <= 0;
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end
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else
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begin
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dout <= {sign_bit,{10{!sign_bit}}};
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ovrflw <= 1;
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end
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reg din_nd_d1 = 0;
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always @(posedge clk) begin
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din_nd_d1 <= din_nd;
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dout_nd <= din_nd_d1;
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end
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endmodule
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