91 lines
2.8 KiB
Verilog
91 lines
2.8 KiB
Verilog
`timescale 1ns / 1ns
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// * Engineer:
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// * *************************************************** *
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// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
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// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║ ██║ *
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// * ███╔╝ ██║ ██║██████╔╝██║ ██║██║ ███╗███████║ *
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// * ███╔╝ ██║ ██║██╔══██╗██║ ██║██║ ██║██╔══██║ *
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// * ███████╗╚██████╔╝██║ ██║╚██████╔╝╚██████╔╝██║ ██║ *
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// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
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// * *************************************************** *
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// * Update Date:
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// * NOTE : this is the first version convert from wider bitwidth to narrower bitwidth
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module width_convert #(
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parameter INPUT_WIDTH = 32,
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parameter OUTPUT_WIDTH = 1
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) (
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input clk,
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input rst,
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input data_in_valid,
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output wire data_in_ready,
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input wire [INPUT_WIDTH - 1 : 0] data_in,
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output reg data_out_valid,
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output reg [OUTPUT_WIDTH -1 : 0] data_out
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);
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localparam CNT_MAX = INPUT_WIDTH / OUTPUT_WIDTH;
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// ******** Wire & Reg ********
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reg [ INPUT_WIDTH-1:0] data_in_latch;
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reg [$clog2(CNT_MAX) - 1 : 0] cnt;
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reg flag_working;
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// ******** Assingment ********
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assign data_in_ready = (~flag_working & ~rst) | (cnt == CNT_MAX - 1);
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// ******** Logic Block ********
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always @(posedge clk) begin
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if (rst) begin
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data_in_latch <= 'd0;
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end
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else begin
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if (data_in_valid && data_in_ready) begin
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data_in_latch <= data_in;
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end
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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flag_working <= 0;
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end
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else if (data_in_valid) begin
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flag_working <= 1;
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end
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else if (cnt == CNT_MAX - 1) begin
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flag_working <= 0;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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cnt <= 0;
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end
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else if (flag_working) begin
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cnt <= cnt + 1;
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end
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end
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always @(*) begin
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data_out = data_in_latch[cnt*OUTPUT_WIDTH+OUTPUT_WIDTH-1-:OUTPUT_WIDTH];
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data_out_valid = flag_working;
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end
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// ******** Inst ********
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// ******** Debug ********
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endmodule
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