78 lines
2.0 KiB
Verilog
78 lines
2.0 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/04/15 20:17:12
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// Design Name:
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// Module Name: tb_Receiver
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_Receiver ();
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reg clk;
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reg clk_2x;
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reg clk_4x;
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reg rst;
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localparam CLK_PERIOD = 20_0;
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always #(10) clk = ~clk;
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always #(5) clk_2x = ~clk_2x;
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always #(2.5) clk_4x = ~clk_4x;
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// * start
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reg [11:0] ad9361_rx_data_i;
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reg [11:0] ad9361_rx_data_q;
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reg flag;
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reg [11:0] mem_i [10000:0];
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reg [11:0] mem_q [10000:0];
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initial begin
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clk <= 1'b0;
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clk_2x <= 1'b0;
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clk_4x <= 1'b0;
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$readmemb("D:/WorkSpace/IC/SIP/ToLYY/ToLYY/MM20/MM20.srcs/sim_1/new/ad9361_i_testbench.txt", mem_i);
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$readmemb("D:/WorkSpace/IC/SIP/ToLYY/ToLYY/MM20/MM20.srcs/sim_1/new/ad9361_q_testbench.txt", mem_q);
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rst <= 1'b0;
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flag <= 0;
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#(CLK_PERIOD * 50) rst <= 1;
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#(CLK_PERIOD * 10) rst <= 0;
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#(CLK_PERIOD * 100) flag <= 1;
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end
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Receiver u_Receiver (
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.clk (clk),
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.clk_2x (clk_2x),
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.clk_4x (clk_4x),
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.rst (rst),
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.speed_mode (3'd0),
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.ad9361_rx_data_i(ad9361_rx_data_i),
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.ad9361_rx_data_q(ad9361_rx_data_q)
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);
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reg [15:0] index = 16'd0;
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always @(posedge clk) begin
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if (rst) begin
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index <= 'd0;
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ad9361_rx_data_i <= 'd0;
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ad9361_rx_data_q <= 'd0;
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end
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else if (flag) begin
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ad9361_rx_data_i <= mem_i[index];
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ad9361_rx_data_q <= mem_q[index];
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index <= index + 16'd1;
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end
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end
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endmodule
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