56 lines
1.0 KiB
Verilog
56 lines
1.0 KiB
Verilog
`timescale 1ns / 1ns
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module tb_add_prefix ();
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reg clk = 0;
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reg rst = 0;
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always #1 clk <= ~clk;
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reg start;
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wire ready;
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reg [31:0] data_in = 0;
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wire [31:0] data_out;
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wire data_out_valid;
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initial begin
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#20 rst <= 1'b1;
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#20 rst <= 0;
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start <= 1'b0;
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#100 start <= 1'b1;
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#2 start <= 1'b0;
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end
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add_prefix #(
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.WIDTH (32),
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.DATA_LEN (256),
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.PREFIX_LEN(8)
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) u_add_prefix (
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.clk (clk),
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.start (start),
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.ready (ready),
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.data_in (data_in),
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.data_in_ready (data_in_ready),
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.data_out (data_out),
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.data_out_valid(data_out_valid)
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);
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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data_in <= 0;
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end
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else if (start || data_in > 0) begin
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data_in <= data_in + 32'd1;
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end
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else begin
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data_in <= 0;
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end
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end
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endmodule
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