111 lines
2.7 KiB
Verilog
111 lines
2.7 KiB
Verilog
`timescale 1ns / 1ns
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module tb_enc_control ();
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reg clk = 1;
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reg rst = 1;
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always #1 clk <= ~clk;
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reg intr = 0;
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reg s_axis_fifo_tvalid = 1'b0;
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wire s_axis_fifo_tready;
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reg [31:0] s_axis_fifo_tdata;
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reg [31:0] data_src_count;
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wire enc_dout_intr;
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wire enc_dout_valid;
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wire [15:0] enc_dout;
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reg fifo_enc_out_rd_en;
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wire [31:0] fifo_enc_out_dout_map;
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wire fifo_enc_out_empty;
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reg [ 1:0] cnt_div = 0;
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wire clk_div;
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assign enc_dout_valid = ~fifo_enc_out_empty;
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assign clk_div = cnt_div[1];
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initial begin
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#100 rst <= 1'b0;
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end
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reg [31:0] cnt_start;
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always @(posedge clk) begin
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if (rst) begin
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cnt_start <= 0;
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s_axis_fifo_tvalid <= 0;
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end
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else if (cnt_start < 70) begin
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cnt_start <= cnt_start + 1;
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s_axis_fifo_tvalid <= 0;
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end
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else if (cnt_start < 1500) begin
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cnt_start <= cnt_start + 1;
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s_axis_fifo_tvalid <= 1;
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end
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else if (cnt_start < 25000) begin
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cnt_start <= cnt_start + 1;
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s_axis_fifo_tvalid <= 0;
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end
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else if (cnt_start < 50000) begin
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cnt_start <= cnt_start + 1;
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s_axis_fifo_tvalid <= 1;
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end
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else begin
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s_axis_fifo_tvalid <= 0;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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data_src_count <= 0;
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s_axis_fifo_tdata <= $random();
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end
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else begin
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if (s_axis_fifo_tready) begin
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s_axis_fifo_tdata <= $random();
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end
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data_src_count <= 1000;
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end
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end
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enc_control u_enc_control (
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.clk (clk),
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.rst (rst),
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.s_axis_fifo_tvalid (s_axis_fifo_tvalid),
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.s_axis_fifo_tready (s_axis_fifo_tready),
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.s_axis_fifo_tdata (s_axis_fifo_tdata),
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.data_src_count (data_src_count),
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.fifo_enc_out_rd_clk (clk_div),
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.fifo_enc_out_rd_en (fifo_enc_out_rd_en),
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.fifo_enc_out_dout_map(fifo_enc_out_dout_map),
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.fifo_enc_out_empty (fifo_enc_out_empty)
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);
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reg [1:0] cnt_rd;
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always @(posedge clk_div) begin
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if (rst) begin
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cnt_rd <= 0;
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end
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else begin
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if (enc_dout_valid) cnt_rd <= cnt_rd + 1;
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end
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end
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always @(posedge clk_div) begin
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if (cnt_rd == 2'b11) fifo_enc_out_rd_en <= 1;
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else fifo_enc_out_rd_en <= 0;
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end
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always @(posedge clk) begin
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cnt_div <= cnt_div + 1;
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end
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endmodule
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