54 lines
1.3 KiB
Verilog
54 lines
1.3 KiB
Verilog
`timescale 1ns / 1ns
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module tb_scrambler ();
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reg clk = 0;
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always #1 clk <= ~clk;
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reg [3:0] cnt_startup = 0;
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reg rst;
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always @(posedge clk) begin
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if (cnt_startup < 4'hF) begin
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cnt_startup <= cnt_startup + 1;
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end
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rst <= cnt_startup <= 4'hC;
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end
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reg [31:0] s_axis_tdata;
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reg s_axis_tvalid;
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wire s_axis_tready;
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reg s_axis_tlast;
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wire [31:0] m_axis_tdata;
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wire m_axis_tvalid;
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// wire m_axis_tvalid;
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wire m_axis_tlast;
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reg [31:0] cnt = 0;
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always @(posedge clk) begin
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s_axis_tvalid <= (cnt_startup == 4'hF && cnt < 32);
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if (rst) begin
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s_axis_tdata <= 0;
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end
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else if (s_axis_tready && cnt < 32) begin
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s_axis_tdata <= cnt;
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cnt <= cnt + 1;
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end
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end
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scrambler u_scrambler (
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.clk (clk),
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.rst (rst),
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.s_axis_tdata (s_axis_tdata),
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.s_axis_tvalid(s_axis_tvalid),
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.s_axis_tready(s_axis_tready),
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.s_axis_tlast (s_axis_tlast),
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.m_axis_tdata (m_axis_tdata),
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.m_axis_tvalid(m_axis_tvalid),
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.m_axis_tready(1),
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.m_axis_tlast (m_axis_tlast)
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);
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endmodule
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