91 lines
2.0 KiB
Verilog
91 lines
2.0 KiB
Verilog
`timescale 1ns / 1ns
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module tb_width_convert ();
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reg clk = 1;
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reg rst = 1;
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always #(2) clk <= ~clk;
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initial begin
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#10 rst <= 1'b0;
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end
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reg [31:0] data_in;
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reg data_in_valid;
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wire data_in_ready;
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wire data_out_valid;
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wire [ 0:0] data_out;
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width_convert #(
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.INPUT_WIDTH (32),
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.OUTPUT_WIDTH(1)
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) u_width_convert (
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.clk (clk),
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.rst (rst),
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.data_in_valid (data_in_valid),
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.data_in_ready (data_in_ready),
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.data_in (data_in),
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.data_out_valid(data_out_valid),
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.data_out (data_out)
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);
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reg [5:0] cnt_startup;
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reg [3:0] cnt_data_in;
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always @(posedge clk) begin
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if (rst) begin
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cnt_startup <= 0;
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end
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else if (cnt_startup < 6'b111111) begin
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cnt_startup <= cnt_startup + 1;
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end
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end
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reg [5:0] cnt_in;
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localparam CNT_IN_MAX = 32;
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always @(posedge clk) begin
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if (rst) begin
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cnt_in <= 0;
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end
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else if (cnt_in == CNT_IN_MAX) begin
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cnt_in <= 0;
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end
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else begin
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cnt_in <= cnt_in + 1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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data_in <= $random();
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cnt_data_in <= 0;
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end
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else if (cnt_startup == 6'b111111 && cnt_in == CNT_IN_MAX && cnt_data_in < 5) begin
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data_in <= $random();
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cnt_data_in <= cnt_data_in + 1;
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end
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end
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always @(posedge clk) begin
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// if (cnt_startup == 6'b111111 && cnt_in == CNT_IN_MAX) begin
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// data_in_valid <= 1;
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// end
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// else begin
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// data_in_valid <= 0;
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// end
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if (rst) begin
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data_in_valid <= 0;
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end
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else if (cnt_startup == 6'b111_111 && cnt_data_in < 5) begin
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data_in_valid <= 1;
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end
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else begin
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data_in_valid <= 0;
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end
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end
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endmodule
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